Abstract: Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer.

Abstract: Provided is a method for running cache invalidation in a computer system including: checking whether or not the cache invalidation is in a range mode when the cache invalidation is started; resetting an internal count associated with the invalidation if the cache invalidation is in the range mode; accessing a cache entry; checking whether or not a tag is ‘hit’ as a result of the accessing to the cache entry; checking whether or not a state of the cache is dirty if the tag is ‘hit’; performing write operation on the memory and clearing the cache entry if the state of the cache is dirty; clearing the cache entry if the state of the cache is not dirty; incrementing the internal count by 1 if the tag is not ‘hit’ or if the cache entry is cleared; and ending the cache invalidation if the internal count exceeds a predetermined offset.

Abstract: Provided is a method of decoding instructions in a microprocessor, including: checking existence of instructions when instruction decoding is stared; folding two instructions when two instructions exist; and decoding folded instructions. Accordingly, it is possible to improve performance in a microprocessor by generating one instruction by folding two instructions into one instruction in an instruction decoding period.

Abstract: Disclosed is a method of operating an immediate value in an extendable instruction set computer (EISC) processor, comprising: checking whether or not an unsigned immediate value is used to generate an extension register (ER) value for operating an immediate value; and generating the ER value by performing zero extension for the unsigned immediate value using an unsigned load extension register with immediate (ULERI) instruction if the unsigned immediate value is used. It is possible to improve operational efficiency by preventing an LERI instruction from being unnecessarily executed when an immediate value is operated using a 16-bit instruction in the EISC processor.

Abstract: Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer.

Abstract: Provided is a Java bytecode translating method which includes: a bytecode fetch step (S1 10) that fetches a Java bytecode from a Java class file; a static field address detection and data processing step (S140) which gains access to a field (130) according to a first field address (FA1) and processes data; a static field address storage step (S 150) that stores a first upper field address (FAU1) including upper bits among bits of the first field address (FA1) in a first storage portion (110), and which stores a first lower field address (FAD1) including remainder lower bits excluding the first upper field address (FAU1) among the bits of the first field address (FA1) in an operand field (120b); a static operation code translating step (S 160) that translates an operation code stored in an operation code field (120a) into a new static field accessing operation code (NOPA); a first field address creation step (S240) that creates a second field address (FA2); and a first data processing step (S250) that gains ac

Abstract: Disclosed is a data security system using a USB device for maintaining security for files made while various kinds of application programs are used. The data security system comprises: a local computer having the various kinds of application programs installed therein and performing various works by executing the installed various kinds of application programs; and a USB device connected to the local computer via a USB communicating means, wherein, when the USB device is connected to the local computer, a security program is automatically installed from the USB device into the local computer, and the automatically-installed security program performs a security service for works in the local computer.

Abstract: Disclosed are a computer display monitoring apparatus, a system including the same, and a computer display monitoring method. The computer display monitoring system includes a computer terminal; a monitor; and a display monitoring apparatus provided between the computer terminal and the monitor for capturing a video signal transmitted from the computer terminal to the monitor, the display monitoring apparatus including a first coupler and a second coupler.

Abstract: A central processing unit (CPU) for easily testing and debugging an application program, which includes a data communications unit for performing data communications with a host computer, a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state, a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program, and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.

Abstract: A central processing unit (CPU) for easily testing and debugging an application program, which includes a data communications unit for performing data communications with a host computer, a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state, a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program, and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.