Patents Assigned to Advanced Micro Devices, Incs.
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Publication number: 20240114105Abstract: A processing device and method for executing a color twist operation are provided. The processing device comprises memory and a processor configured to convert values of pixels of a frame from a first color domain to a hue, saturation and value (HSV) color domain, adjust hue values and saturation values of the pixels, store the adjusted hue and saturation values in a portion of the memory local to the processor and convert the frame from the HSV color domain to the first color domain using the adjusted hue and saturation values stored in local memory. The adjusted hue and saturation values are generated from pre-adjusted values, which are generated from masked vector values.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Rajy Meeyakhan Rawther
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Publication number: 20240112747Abstract: A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Tahsin Askar, Naveen Davanam, Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
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Publication number: 20240111420Abstract: Methods, devices, and systems for retrieving information based on cache miss prediction. It is predicted, based on a history of cache misses at a private cache, that a cache lookup for the information will miss a shared victim cache. A speculative memory request is enabled based on the prediction that the cache lookup for the information will miss the shared victim cache. The information is fetched based on the enabled speculative memory request.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, John Kalamatianos
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Publication number: 20240111674Abstract: Data reuse cache techniques are described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and is also stored to a data reuse cache communicatively coupled between the load-store unit and the execution unit. Upon receipt of a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Alok Garg, Neil N Marketkar, Matthew T. Sobel
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Publication number: 20240111680Abstract: Selecting between basic and global persistent flush modes is described. In accordance with the described techniques, a system includes a data fabric in electronic communication with at least one cache and a controller configured to select between operating in a global persistent flush mode and a basic persistent flush mode based on an available flushing latency of the system, control the at least one cache to flush dirty data to the data fabric in response to a flush event trigger while operating in the global persistent flush mode, and transmit a signal to switch control to an application to flush the dirty data from the at least one cache to the data fabric while operating in the basic persistent flush mode.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Alexander Joseph Branover
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Publication number: 20240111421Abstract: Connection modification based on traffic pattern is described. In accordance with the described techniques, a traffic pattern of memory operations across a set of connections between at least one device and at least one memory is monitored. The traffic pattern is then compared to a threshold traffic pattern condition, such as an amount of data traffic in different directions across the connections. A traffic direction of at least one connection of the set of connections is modified based on the traffic pattern corresponding to the threshold traffic pattern condition.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Nathaniel Morris, Kevin Yu-Cheng Cheng, Atul Kumar Sujayendra Sandur, Sergey Blagodurov
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Publication number: 20240112720Abstract: A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing CA signals to the memory, and a second group of driver circuits providing DQ signals to the memory. A plurality of the conductive traces which carry the DQ signals are constructed with a length longer than that of conductive traces carrying the reference clock signal in order to reduce an effective insertion delay associated with coupling the reference clock signal to latch respective incoming DQ signals.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Aaron D Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
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Publication number: 20240111355Abstract: Methods and systems are disclosed for reducing power consumption by a system including a digital unit and an optical unit. Techniques disclosed comprise generating a workload signature of an incoming workload to be executed by the system. Based on the generated workload signature, techniques disclosed comprise matching the incoming workload with a profile of stored workload profiles. The workload profiles are generated by a trace capture unit. Based on the associated profile, a task submission transaction is sent to the optical unit of the system, representative of a request to execute the incoming workload by the optical unit.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Kevin Y. Cheng, SeyedMohammad SeyedzadehDelcheh, Masab Ahmad
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Publication number: 20240111688Abstract: A technique for servicing a memory request is disclosed. The technique includes obtaining permissions associated with a source and a destination specified by the memory request, obtaining a first set of address translations for the memory request, and executing operations for a first request, using the first set of address translations.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Omar Fakhri Ahmed, Norman Vernon Douglas Stewart, Mihir Shaileshbhai Doctor, Jason Todd Arbaugh, Milind Baburao Kamble, Philip Ng, Xiaojian Liu
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Publication number: 20240111425Abstract: A method for operating a memory having a plurality of banks accessible in parallel, each bank including a plurality of grains accessible in parallel is provided. The method includes: based on a memory access request that specifies a memory address, identifying a set that stores data for the memory access request, wherein the set is spread across multiple grains of the plurality of grains; and performing operations to satisfy the memory access request, using entries of the set stored across the multiple grains of the plurality of grains.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, Marko Scrbak
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Publication number: 20240112392Abstract: Devices and methods for node traversal for ray tracing are provided, which comprise casting a first ray in a space comprising objects represented by geometric shapes, traversing, for the first ray, at least one first node of an accelerated hierarchy structure representing an approximate volume of a group of the geometric shapes and a second node representing a volume of one of the geometric shapes, casting a second ray in the space, selecting, for the second ray, a starting node of traversal based on locations of intersection of the first ray and the second ray and an identifier which identifies one or more nodes intersected by the first ray and traversing, for the second ray, the accelerated hierarchy structure beginning at the starting node of traversal.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: David William John Pankratz, Konstantin I. Shkurko
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Publication number: 20240112749Abstract: The disclosed computing device includes a cache memory and at least one processor coupled to the cache memory. The at least one processor is configured to copy data written to one or more nonredundant wordlines of the cache memory to one or more redundant wordlines of the cache memory. The at least one processor is additionally configured to detect a mismatch between data read from the one or more nonredundant wordlines and data stored in the one or more redundant wordlines. The at least one processor is also configured to perform a remediation action in response to detecting the mismatch. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Patrick James Shyvers
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Publication number: 20240112297Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to determine, for an input tile of an image, a receptive field via backward propagation and determine a size of the input tile based on the receptive field and an amount of local memory allocated to store data for the input tile. The processor determines whether the amount of local memory allocated to store the data of the input tile and padded data for the receptive field.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Tung Chuen Kwong, Ying Liu, Akila Subramaniam
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Publication number: 20240112722Abstract: A memory controller for generating accesses for a memory includes a row hammer logic circuit for providing a sample request. In response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row. In response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Kevin M. Brandl, James R. Magro, Kedarnath Balakrishnan, Jing Wang
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Publication number: 20240111676Abstract: A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: John Kalamatianos, Marko Scrbak, Gabriel H. Loh, Akhil Arunkumar
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Publication number: 20240111622Abstract: A disclosed method can include (i) reporting, by a microcontroller, detection of a violation of a physical infrastructure constraint to a machine check architecture, (ii) triggering, by the machine check architecture in response to the reporting, a machine-check exception such that the violation of the physical infrastructure constraint is recorded, and (iii) performing a corrective action based on the triggering of the machine-check exception. Various other apparatuses, systems, and methods are also disclosed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, IncInventors: Siddharth K. Shah, Vilas Sridharan, Amitabh Mehra, Anil Harwani, William Fischofer
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Publication number: 20240111684Abstract: The disclosed method includes detecting a stalled memory request, for a first level cache within a cache hierarchy of a processor, that includes an outstanding memory request associated with a second level cache within the cache hierarchy that is higher than the first level cache. The method further includes indicating, to the second level cache, that the first level cache is experiencing a starvation issue due to stalled memory requests to enable the second level cache to perform starvation-remediation actions. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Sankaranarayanan Gurumurthy, Anil Harwani
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Publication number: 20240111677Abstract: A method for performing prefetching operations is disclosed. The method includes storing a recorded access pattern indicating a set of accesses for a region; in response to an access within the region, fetching the recorded access pattern; and performing prefetching based on the access pattern.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Gabriel H. Loh, Marko Scrbak, Akhil Arunkumar, John Kalamatianos
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Publication number: 20240111591Abstract: Portions of programs, oftentimes referred to as kernels, are written by programmers to target a particular type of compute unit, such as a central processing unit (CPU) core or a graphics processing unit (GPU) core. When executing a kernel, the kernel is separated into multiple parts referred to as workgroups, and each workgroup is provided to a compute unit for execution. Usage of one type of compute unit is monitored and, in response to the one type of compute unit being idle, one or more workgroups targeting another type of compute unit are executed on the one type of compute unit. For example, usage of CPU cores is monitored, and in response to the CPU cores being idle, one or more workgroups targeting GPU cores are executed on the CPU cores.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Bradford Michael Beckmann, Sooraj Puthoor
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Publication number: 20240111618Abstract: A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. The sampled signals are de-serialized to provide sets of symbols. A start of a symbol period is determined in response to detecting that a given sample is different from a prior sample, and the prior sample indicates no error. The sets of symbols are filtered to provide corresponding output symbols based on the start.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Aaron D. Willey, Karthik Gopalakrishnan, Pradeep Jayaraman, Ramon Mangaser
