Abstract: The disclosure is directed to a multiprocessor data processing system. The data processing system of the invention generally comprises a plurality of microprocessor units and an instruction memory device electrically storing a common set of instructions in a pre-ordered sequence, each of said instructions being stored in representative, digital, electrical signal form. A tapped delay line instruction bus system is provided to electrically interconnect the instruction memory with each of the microprocessor units. The tapped delay line instruction bus system includes a plurality of individual tap buses and electrical controls operable to apply the digital electrical signals for each of the instructions stored in the instruction memory device to each of the individual tap buses, one tap bus at a time, in a timed, time-skewed sequence.