Abstract: A SiC die with Os and/or W/WC/TiC contacts and metal conductors is encapsulated either alone or on a ceramic substrate using a borosilicate (BSG) glass that is formed at a temperature well below upper device operating temperature limits but serves as a stable protective layer above the operating temperature (over 1000° C., preferably >1200° C.). The glass is preferably 30-50% B2O3/70-50% SiO2, formed by reacting a mixed powder, slurry or paste of the components at 460°-1000° C. preferably about 700° C. The die can be mounted on the ceramic substrate using the BSG as an adhesive. Metal conductors on the ceramic substrate are also protected by the BSG. The preferred ceramic substrate is AlN but SiC/AlN or Al2 03 can be used.
Type:
Application
Filed:
June 15, 2005
Publication date:
December 29, 2005
Applicant:
Advanced Power Technology, Inc., a Delaware corporation
Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The dies are mounted on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate. A source of each die is electrically connected to a second area of the conductive layer on the substrate. A gate of each die is electrically connected to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.
Type:
Application
Filed:
June 3, 2005
Publication date:
October 6, 2005
Applicant:
Advanced Power Technology, Inc., a Delaware corporation
Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.
Type:
Application
Filed:
January 13, 2004
Publication date:
August 26, 2004
Applicant:
Advanced Power Technology, Inc., a Delaware corporation
Abstract: The invention proposes a single stage, single switch, input-output isolated converter configuration using a hybrid combination of forward and flyback converters. The converter operates at a high input power factor with a regulated DC output voltage. It makes use of a novel control scheme utilizing duty cycle control at two discrete operating frequencies. Although the invention employs two frequencies, it does not use a continuous frequency variation. The proposed configuration has the advantage of reduced peak current stresses on the components and is specifically suited for ‘buck’ applications where low DC output voltages (e.g. 24V, 48V) are needed. The proposed configuration will be of specific interest to industries associated with battery charging and uninterruptible power supply (UPS) systems.
Type:
Application
Filed:
October 20, 2003
Publication date:
July 15, 2004
Applicant:
ADVANCED POWER TECHNOLOGY, INC., a Delaware corporation
Inventors:
Vivek Agarwal, Victor Prince Sundarsingh, Serge Bontemps, Alain Calmels
Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.
Type:
Application
Filed:
January 27, 2003
Publication date:
July 31, 2003
Applicant:
ADVANCED POWER TECHNOLOGY, INC., a Delaware corporation
Abstract: A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.
Type:
Application
Filed:
February 22, 2002
Publication date:
June 20, 2002
Applicant:
ADVANCED POWER TECHNOLOGY, INC., Delaware corporation
Inventors:
Dah Wen Tsang, John W. Mosier, Douglas A. Pike, Theodore O. Meyer