Abstract: A data processing apparatus and method are described in which a CPU is operable in either a main processing mode (User32) or an exception processing mode (e.g. FIQ32). The CPU has a plurality of main data registers (R0 to R15) and a processing status register (CPSR) for use in the main processing mode. Upon entering the exception processing mode at least one exception data register (R8fiq to R14fiq) is substituted for use in place of a respective corresponding one of the main data registers and the data held within the processing status register is stored within a saved processing status register (SPSRfiq). When the exception processing mode is left, the main data registers are returned for use in place of the exception data registers and the data stored within the saved processing status register is restored to the processing status register. A plurality of exception processing modes are described each having their own associated exception data registers.

Abstract: A data memory and a method of reading a data memory are described. Data words (Word0, Word1, Word2, Word3) are stored within the data memory within an array of memory cells arranged in columns and rows. A particular data word within a memory cell is accessed by activating a complete row (2) to output the data words within all columns of that row and then selecting the data word from the appropriate column with a data word selection multiplexer (6). An amplifier (8) is used to reduce the time taken for data signals read from the array to reach readable values. In order to save power, the amplifier is disabled during a second and subsequent successive reading operations from a row that has already been activated. Precharging of a output lines is also disabled for second and subsequent successive readings from a row.