Abstract: A semiconductor package includes a dielectric layer, a plurality of traces, a plurality of electrical pads, a plurality of studs and at least a semiconductor device. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The traces are disposed in the dielectric layer and are exposed on the second dielectric surface. The electrical pads are disposed on the first dielectric surface. The studs are disposed in the dielectric layer and are exposed on the first dielectric surface. The studs are electrically connected to the traces and the electrical pads. The semiconductor device is disposed on the second dielectric surface and electrically connected to the traces.

Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.

Abstract: A substrate structure includes first, second and third metal layers embedded in a dielectric layer between its opposite upper first and lower second surfaces. The entire upper surface of the first metal layer is exposed on the first surface of the dielectric layer, the entire lower surface of the third metal layer is exposed on the second surface of the dielectric layer, and the second metal layer is disposed between the first metal layer and the third metal layer, wherein the area of the third metal layer is larger than the area of the second metal layer.

Abstract: A semiconductor element that includes a forsy patterned conductive layer, a second pattern conductive layer and an insulating layer. The first surface of the second patterned conductive layer is connected to a second surface of the first patterned conductive layer. The insulating layer includes at least one space on a second surface thereof. The first patterned conductive layer and the second patterned conductive layer are embedded in the insulating layer between a first surface and a second surface thereof, the first surface of the first patterned conductive layer is entirely exposed on a first surface of the insulating layer, a second surface of the second patterned conductive layer is entirely exposed on the second surface of the insulating layer, and the space exposes the second surface of the first patterned conductive layer.

Abstract: A method of manufacturing a semiconductor element is provided. The method includes the following steps. A carrier and a mold are provided. A first patterned conductive layer including a plurality of traces is formed on the carrier. A second patterned conductive layer is formed on the first patterned conductive layer. The carrier is disposed with the mold to form at least one mold cavity. The mold cavity is infused with a molding material. The molding material fills the mold cavity to encapsulate the first and second patterned conductive layers. The carrier is removed by etching to expose the plurality of traces embedded in the molding material without affecting the width of the traces.

Abstract: A semiconductor structure and a method of fabricating the same. The semiconductor structure comprises: a layer element, one or more supporting elements disposed on a first surface of the layer element, and one or more anchoring elements disposed within the layer element and connected to the one or more supporting elements to couple the one or more supporting elements to the layer element to strengthen the layer element.

Abstract: The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.

Abstract: A manufacturing method includes the follow steps. Firstly, a carrier is provided. Then, a plurality of traces are formed on the carrier. Then, a trace molding compound layer is formed on the carrier by a first molding process. Then, the carrier is removed from the trace molding compound layer to expose an etched surface of the trace molding compound layer and trace upper surfaces of the traces. Then, at least a chip is disposed on the etched surface of the trace molding compound layer and the chip is connected to the trace upper surfaces. Then, a chip molding compound layer is formed on the etched surface by a second molding process substantially similar to the first molding process, wherein the chip molding compound layer and the trace molding compound layer are formed of substantially the same molding compound material.

Abstract: The present invention describes two systems (100, 300) for encapsulation of semiconductor dies. Both systems (100, 300) involve attaching an encapsulation spacer (102, 302, 302a, 302b) having one or more apertures (104, 304) on an associated substrate (150) so that a group of chips is located within the aperture (104, 304). The first system (100) involves dispensing encapsulant (103) directly into an aperture. The second system (300) involves attaching an encapsulant delivery layer (350, 351) onto the encapsulation spacer and discharging encapsulant into an aperture via a recessed gate (308).

Abstract: A manufacturing method of semiconductor substrate includes following steps: providing a base layer; forming a plurality of traces on the base layer; forming a plurality of studs correspondingly on the traces; forming a molding material layer on the base layer to encapsulate the traces and studs; forming a concave portion on the molding material layer; and, removing the base layer.

Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.

Abstract: A semiconductor package, a substrate and a manufacturing method thereof are provided. The substrate comprises a conductive carrier, a first metal layer and a second metal layer. The first metal layer is formed on the conductive carrier and comprises an lead pad having an upper surface. The second metal layer is formed on the first metal layer and comprises a bond pad. The bond pad overlaps and is in contact with the upper surface of the first metal layer. The upper surface of the lead pad is partially exposed. A part of the bond pad overhang outward from the edge of the lead pad.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed on the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is more than 1.2 times the second dimension. The top part is composed of solder and will melt under a pre-determined temperature. The pillar part will not melt under the pre-determined temperature.

Abstract: A package structure including a first semiconductor element, a second semiconductor element, a semiconductor interposer and a substrate is provided. The first semiconductor element includes multiple first conductive bumps. The second semiconductor element includes multiple second conductive bumps. The semiconductor interposer includes a connection motherboard, at least one signal wire and at least one signal conductive column. The signal wire is disposed on the connection motherboard. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps respectively. The signal conductive column is electrically connected to the signal wire. The substrate is electrically connected to the signal conductive column. The first and the second semiconductor elements have the same circuit structure. The substrate of the package structure can simultaneously form a signal communication path with the first and the second semiconductor element respectively.

Abstract: The invention discloses a package structure including a semiconductor device, a first protection layer, a second protection layer and at least one conductive connector. The semiconductor device has at least one pad. The first protection layer is disposed on the semiconductor device and exposes the pad. The second protection layer, disposed on the first protection layer, has at least one first opening and at least one second opening. The first opening exposes a partial surface of the pad. The second opening exposes a partial surface of the first protection layer. The conductive connector, opposite to the pad, is disposed on the second protection layer and coupled to the pad through the first openings.

Abstract: The semiconductor device carrier comprises a conductive carrier, a dielectric layer, a conductive trace layer, a conductive stud layer and the plating conductive layer. The conductive carrier comprises at least one cavity. The dielectric layer has a first dielectric surface and a second dielectric surface opposite the first dielectric surface. The conductive trace layer disposes in the dielectric layer and is exposed on the second dielectric surface. The conductive stud layer disposes in the dielectric layer and is exposed on the first dielectric surface, wherein the conductive stud layer is electrically connected to the conductive trace layer. The plating conductive layer is disposed on the first dielectric surface and the exposed conductive stud layer. The cavity exposes the conductive trace layer and the dielectric layer.

Abstract: A manufacturing method of semiconductor substrate includes following steps: providing a base layer; forming a plurality of traces on the base layer; forming a plurality of studs correspondingly on the traces; forming a molding material layer on the base layer to encapsulate the traces and studs; forming a concave portion on the molding material layer; and, removing the base layer.

Abstract: A conductive carrier having a first surface and a second surface is provided. The conductive trace layer is formed on the second surface of the conductive carrier. A conductive stud layer is formed on the conductive trace layer. A dielectric layer is formed on the conductive layer to encapsulate the conductive trace layer and the conductive stud layer. The conductive stud layer is exposed. A plating conductive layer is formed to envelop the conductive carrier, the dielectric layer and the exposed end of the conductive stud layer. A cavity is formed on the conductive carrier, wherein the conductive trace layer and the dielectric layer are exposed in the cavity. A surface finishing is formed on at least an exposed portion of the conductive stud layer. The plating conductive layer is removed.

Abstract: A semiconductor substrate including a carrier, a first conductive layer and a second conductive layer is disclosed. The carrier has a first surface, a second surface, and a concave portion used for receiving a semiconductor element. The first conductive layer is embedded in the first surface and forms a plurality of electric-isolated package traces. The second conductive layer is embedded in the second surface and electrically connected to the first conductive layer. The semiconductor substrate can be applied to a semiconductor package for carrying a semiconductor chip, and combined with a filling structure for fixing the chip. Furthermore, a plurality of the semiconductor substrates can be stacked and connected via adhesive layers, so as to form a semiconductor device with a complicated structure.