Abstract: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

Abstract: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.

Abstract: In a method of forming an electrical circuit assembly, a substrate is provided including a plurality of first segments that form an electrical circuit. The first segments have surfaces that rise above surfaces of other segments that form the electrical circuit. All of the segments are deposited on the substrate via one or more shadow mask vapor deposition processes in a vacuum. A photoresist caused to cover all of the segments is hardened and then abraded until surfaces of the first segments are exposed, but surfaces of the other segments are not exposed, and a surface of the abraded photoresist is at the same level as the exposed surfaces of the first segments. Second segments can be deposited on the exposed surfaces of the first segments via a shadow mask vapor deposition process in a vacuum to a level above the top surface of the abraded photoresist.

Abstract: A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.

Abstract: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.

Abstract: In a system and method of dimensional adjustment or positioning of an aperture mask for depositing a pattern of material on a substrate, an aperture mask is coupled to a frame such that the frame does not block one or more deposition apertures of the aperture mask. An external force applied to the frame causes the frame to move or bend and place the aperture mask in tension or compression thereby adjusting at least one dimension of the aperture mask or a position of at least one deposition aperture.

Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.

Abstract: In a method of preparing and using an aperture mask, a temperature of an aperture mask is increased to a first, mounting temperature (T1), whereupon the size of the aperture mask increases according to its coefficient of thermal expansion (CTEam), until at least one dimension thereof is of a first desired extent. The temperature of a frame is also increased to T1, whereupon the size of the frame grows according to its coefficient of thermal expansion (CTEf), which is lower than CTEam. The aperture mask is fixedly mounted to the frame at T1. The frame mounted aperture mask is then used for depositing a material on a substrate at a deposition temperature T2 that is less than T1, whereupon the frame holds the shadow mask in tension with the one dimension at a second desired extent.

Abstract: An LCD pixel includes a first conductive segment connected to a first bus, a first insulator segment on the first conductive segment, a second conductive segment on the first insulator segment, a liquid crystal material on the second conductive segment, a third conductive segment on the liquid crystal material, and a thin film transistor having a control terminal, a first power terminal and second power terminal connected to a second bus, a third bus and the second conductive segment, respectively. In response to application of a suitable signal on the second bus when reference voltages are present on the first bus and on the third conductive segment, and a voltage is applied to the third bus, the thin film transistor is operative for charging a capacitor formed by the first conductive segment, the first insulator segment and the second conductive segment and for activating the liquid crystal material.

Abstract: A system and method for improving light extraction from luminescent devices such as light-emitting flat-panel displays (for example, light-emitting diode (OLED) flat-panel displays) or flat panel lamps. The system includes a material with negative index of refraction, preferably with n=?1. The presence of such material on the exit surface of the electro-optic devices such as flat panel display or lamp with light-generating medium sandwiched between materials with refractive index n>1 fully removes TIR and results in light outcoupling efficiency of about 100%.

Abstract: Electronic devices are formed on a substrate that is advanced stepwise through a plurality of deposition vessels. Each deposition vessel includes a source of deposition material and has at least two shadow masks associated therewith. Each of the two masks is alternately positioned within the corresponding deposition vessel for patterning the deposition material onto the substrate through apertures in the mask positioned therein, and positioned in an adjacent cleaning vessel for mask cleaning. The patterning onto the substrate and the cleaning of at least one of the masks are performed concurrently.

Abstract: The present invention is a two-layer shadow mask with small dimension apertures and method of making and using same. The two-layer shadow mask of the present invention is suitable for use for manufacturing an electronic device via deposition in a production system. The two-layer shadow mask of the present invention is formed by a first thick mask, which includes a plurality of apertures that has been formed, for example, by etching, bonded to a second, comparatively thin mask, that has been formed by an electrolytic process, and which includes a plurality of apertures that has been patterned by a photoresist. The second mask is aligned and bonded atop the first mask, with their respective apertures desirably offset one to another. The offset amount of the respective apertures of the two-layer shadow mask determines the resulting final aperture dimension, which may approach 0 microns, through which material is deposited upon a substrate in a deposition production system.

Abstract: In a method of using and cleaning one or more shadow masks of a shadow mask vapor deposition system used to form an electronic device, a substrate is advanced through series connected deposition vacuum vessels. As the substrate advances through each deposition vacuum vessel, material from a material deposition source positioned in the deposition vacuum vessel is deposited on the substrate through a shadow mask positioned therein. The material is also deposited on a surface of the shadow mask that faces the one material deposition source. Following the deposit of material on the surface of the shadow mask in at least one deposition vacuum vessel, a reactive gas is introduced into the deposition vacuum vessel absent the substrate therein. The reactive gas is then ionized to remove the material deposited on the shadow mask.

Abstract: In a method of forming an electrical circuit assembly, a substrate is provided including a plurality of first segments that form an electrical circuit. The first segments have surfaces that rise above surfaces of other segments that form the electrical circuit. All of the segments are deposited on the substrate via one or more shadow mask vapor deposition processes in a vacuum. A photoresist caused to cover all of the segments is hardened and then abraded until surfaces of the first segments are exposed, but surfaces of the other segments are not exposed, and a surface of the abraded photoresist is at the same level as the exposed surfaces of the first segments. Second segments can be deposited on the exposed surfaces of the first segments via a shadow mask vapor deposition process in a vacuum to a level above the top surface of the abraded photoresist.

Abstract: In a method of reducing or undoing progressive threshold shift in a thin-film-transistor (TFT) circuit, first and second voltages applied to source and gate terminals of a first transistor cause the first transistor to conduct and apply the first voltage to the gate terminal of the second transistor. The first voltage applied to the gate terminal of the second transistor coacts with a reference voltage coupled to the source terminal of the second transistor via an LED element to cause the second transistor to not conduct whereupon the LED element does not receive electrical power. After a first predetermined period of time sufficient to reduce or undo a progressive threshold shift in the second transistor, the application of the first voltage to the gate terminal of the second transistor is terminated.

Abstract: A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).

Abstract: A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).

Abstract: A method of improved patterning of indium-tin oxide (ITO) for precision-cutting and aligning a liquid crystal display (LCD) panel includes depositing a transparent ITO layer upon a transparent substrate, depositing a non-transparent plating layer upon the transparent ITO layer and depositing a photoresist layer upon the non-transparent plating layer. The photoresist layer is patterned, exposed and developed to form a plurality of photoresist lines. The photoresist lines are exposed again in an active area only and the plating layer is etched to form a plurality of non-transparent plated lines. The ITO layer is then etched to form a plurality of ITO lines. The photoresist lines are then developed and the non-transparent plated lines are etched away in the active area only. The photoresist that is outside the active area is then removed.

Abstract: The present invention is a multi-layer shadow mask and method of use thereof. The multi-layer shadow mask includes a sacrificial mask bonded to a deposition mask. The sacrificial mask provides protection against an accumulation of evaporant on the deposition mask which would cause the deposition mask to deform.

Abstract: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.