Patents Assigned to AFlash Technology Co., Ltd
  • Patent number: 8937386
    Abstract: The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Tse-Ming Chu, Sung-Chuan Ma
  • Patent number: 8424357
    Abstract: A die includes upper contacts, lower contacts and conductive elements. The upper contacts are formed on an upper face of the die. The upper contacts include a non-connected upper contact and connected upper contacts. The lower contacts are formed on a lower face of the die. The lower contacts include a non-connected lower contact and connected lower contacts. Each of the conductive elements connects a related one of the connected upper contacts to a related one of the connected lower contacts.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: April 23, 2013
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Leo Lu, Kuei-Wu Chu, Jimmy Liang
  • Patent number: 8416576
    Abstract: An integrated circuit card includes a laminate, solder bumps, a die and a package. The laminate includes a core board sandwiched between two conductive layers. The conductive layers are connected to each other with solder bumps filled in apertures defined in the core board. The die is provided on one of the conductive layers. The package is provided on the die and an area of the conductive layer around the die.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: April 9, 2013
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Tse Min Chu, Jimmy Liang
  • Patent number: 8299629
    Abstract: A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: October 30, 2012
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Kuei-Wu Chu, Tse Ming Chu
  • Patent number: 8184464
    Abstract: A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: May 22, 2012
    Assignee: Aflash Technology, Co., Ltd.
    Inventors: Kuei-Wu Chu, Jimmy Liang, Leo Lu
  • Patent number: 8129274
    Abstract: Disclosed is a method for making an aperture in a carrier and electrically connecting two opposite faces of the carrier. At first, a carrier is provided. Secondly, a heater is provided for heating a portion of the carrier in an environment rich in oxygen, thus making an aperture in the carrier and forming an isolative layer on the wall of the aperture synchronously. Finally, the aperture is filled with a conductive material.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: March 6, 2012
    Assignee: Aflash Technology Co., Ltd.
    Inventor: Tse Min Chu
  • Patent number: 7649747
    Abstract: An IC device has a compact design. Capacitors, resistances and inductances are directly integrated in the IC device without packaging in advance. Thus, the IC device obtained has a slim size and an electric apparatus using the IC device has a big space for use.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: January 19, 2010
    Assignee: AFlash Technology Co., Ltd
    Inventor: Sung Chuan Ma
  • Publication number: 20090045520
    Abstract: An IC device has a compact design. Capacitors, resistances and inductances are directly integrated in the IC device without packaging in advance. Thus, the IC device obtained has a slim size and an electric apparatus using the IC device has a big space for use.
    Type: Application
    Filed: June 9, 2008
    Publication date: February 19, 2009
    Applicant: AFLASH TECHNOLOGY CO., LTD.
    Inventor: Sung Chuan MA