Abstract: The present ATM switch includes a plurality of controllers, each of which contains a plurality of cell buffers to store cells for each VC. A plurality of arbitration buffers store pointers, on a VC priority level basis, to order the processing of cell transmissions. The arbitration buffers are processed in priority order, with an interrupt being generated by a timer associated with each arbitration buffer, other than the highest priority arbitration buffer, to ensure that each arbitration buffer is periodically processed.

Abstract: The invention utilizes two-stage shaping and two-priority queuing thereby allowing both shaped and unshaped virtual circuits to be provisioned in a single virtual path. For each VP, a separate dynamic buffer is set up for each shaped VC and unshaped VC within the VP. The shaped cells stored in dynamic buffers are dequeued via VC scheduling (first stage shaper) to a high priority queue according to the shaped VC contracts, and the unshaped cells stored in dynamic buffers are dequeued in a round robin manner to a low priority queue. The outputs of both the high priority queue and the low priority queue are passed to a second stage shaper where cells from the high priority queue are scheduled according to the VP contract, and cells from the low priority queue are also scheduled according to the VP contract, but only when VP bandwidth is not being used by the high priority cells.

Abstract: A modified UTOPIA interface for inter-board applications is provided where the address timing generated by a polling master is extended to be two clock cycles long with no NULL address being driven onto the address line in between addresses. Output and input circuitry is provided in conjunction with the polling master and user ATM boards to accommodate hot insertion and to help drive the circuit. The master preferably includes an outgoing address latch and address latch control associated with the address bus, and a register associated with the enable signal. The master also includes a hot insertion buffer on the incoming cell available signal. The user device(s) include hot insertion buffers on the address bus, the data bus, and the enable signal. A remapping function is also preferably provided in associated with the user board which permits the user board to map received addresses into desired addresses.

Abstract: An ATM switch (10) has a plurality of link controllers (12) each having a FIFO (30) for each VC established, a FIFO (32) for each priority level, and a traffic shaping FIFO (34) for pointers to ABR cells. Cells are pushed into the VC FIFO (30) and a pointer to the VC FIFO (30) is pushed into an arbitration FIFO (32) for the priority level of the VC FIFO (30). Pointers to ABR cells with onward transmission times are pushed into the traffic shaping FIFO (34). The arbitration FIFOs (32) are examined according to a schedule and cells are popped from VC FIFOs (30) according to priority for exit from the controller (12). A leaky bucket processor (22) calculates an average output cell rate OCR and ABR cells are popped from VC FIFOs out of turn if the MCR for the ABR VC exceed the OCR.