Patents Assigned to AIKA DESIGN INC.
  • Patent number: 9287853
    Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: March 15, 2016
    Assignee: AIKA DESIGN INC.
    Inventors: Toru Nakura, Kunihiro Asada
  • Publication number: 20140176205
    Abstract: A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.
    Type: Application
    Filed: May 23, 2012
    Publication date: June 26, 2014
    Applicant: AIKA DESIGN INC.
    Inventors: Toru Nakura, Kunihiro Asada