Abstract: A serial rate conversion circuit converts the serial rate of a stream of signals, for example, from a SONET overhead data link (ODL) rate of 6.48 Mb/s to and from a data communications channel (DCC) rate of 4.096 Mb/s. The circuit includes a low data flow memory and address select circuit for communicating the stream of serial formatted signals at a low data flowrate and a high data flow memory and address select circuit for communicating the stream of serial formatted signals at a high data flowrate. Clock rate conversion circuitry associates between the low data flow memory and address circuit and the high data flow memory and address select circuit to convert the high data flow serial formatted signals back and forth between the low data flowrate and the high data flowrate while maintaining said stream in a serial format.

Abstract: A refresh control system and method for refreshing DRAM memory in a data processing system, such as a communications system, are disclosed. A timer increments a refresh request counter each time that a desired refresh interval elapses. The contents of the refresh request counter is compared with the contents of a burst refresh counter, and a bus request signal generated responsive to the contents differing from one another, such difference indicating that a refresh operation should be performed. The bus arbitration scheme assigns no higher priority to the refresh priority request than for other bus operations; at such time as bus access is granted to the refresh operation, burst refresh is performed until the contents of the burst refresh counter again match the refresh request counter, at which time the bus is released.

Abstract: A method and system for finding a path through a communications matrix represents the assignment of a center stage switch through an input switch to input gates by an input stage array, center stage switch connections between an input stage switch and an output stage switch by a center stage array, and output stage switch connections to output gates by an output stage array, as well as representing idle input switch links to the center stage switches by an idle input array and idle output switch links from the center stage switches by an idle output array.

Abstract: A laser modulation controller (10) modulates the operation of a communications laser circuit and controls the NRZ electrical input into the laser circuit. The electrical modulation controller includes a laser circuit driver (20) for generating and driving input signal to the laser circuit (22). A voltage control circuit (18) controls the laser circuit driver (20) in response to a single input (84). A peak voltage detector circuit (24) responds to the voltage output of the driver circuit (20) and produces a peak voltage signal. A comparison circuit (82) compares the peak voltage signal to a reference signal (78 and 70) and produces from the comparison the control signal input (84) to the voltage control circuit (18). Input circuitry (84) directs the control signal to the voltage control circuit (18) to control the laser circuit driver (20).

Abstract: A desynchronizer for processing pointer movements and stuff bit information associated with payload data transmitted within a synchronous digital communication network. The desynchronizer includes a payload extractor (58) for removing payload data and storing it in an elastic store (32). The extractor also removes the pointer and stuff bit information which is passed through a digital low pass bit leaking module (36). The difference between the write and read addresses of the elastic store is determined (modules 48 and 50) and algebraically combined with the output of the bit leaking module (36) so as to provide the necessary data for adjusting the instantaneous frequency of a variable controlled oscillator (44) that generates the timing base for the read clock for reading the payload from the elastic store in a manner that minimizes jitter.

Abstract: The apparatus (10) includes a laser driver (16) that receives low speed and high speed digital and analog input signals (12, 14), and biases and modulates the laser diode (22) accordingly. The laser driver (16) receives and responds to input from a feedback circuit (36, 38), which includes an average power control portion (36), and a modulation power control portion (38). The average power control portion (36) of the feedback circuit generally determines the DC component of the laser diode output, and compares it to a reference average. The modulation power control portion (38) of the feedback circuit generally determines the maximum and minimum peaks in the laser diode output, takes their average and compares the average to the DC component of the laser output from the average power control portion (36). The laser diode (22) is then driven by the laser driver (16) in response to the comparisons.

Abstract: A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information.

Abstract: Multi-chip module (MCM) (10) includes package body (12) having cavity (20) for accepting a plurality of devices and substrates and seal ring (26) to ensure the integrity of the package. Lead frame (18) having a plurality of individual leads (28) is coupled to the package body (12). Plurality of test points (38) or test pins (30) are located on the external surface of package body (12). A plurality of bond pads are located in cavity (20), including a first set or tier and a second set or tier of bond pads for electrically coupling the devices and substrates in the cavity (20) external to package body (12). The first set or tier of bond pads provides electrical connection between the individual devices in MCM (10) to plurality of test points (38) or test pins (30), and the second set or tier of bond pads provides electrical connection between the individual devices in MCM (10) and plurality of individual leads (28).

Abstract: A laser modulation controller (10) provides laser modulation control by DC bias (54) to a laser (22) with a first control tone (32), amplitude modulating (70) a non-return to zero (NRZ) input working signal (18) to be converted to light output with a second control tone (30), detecting the first control tone from a portion of the light output of the laser (88, 26) as a third signal (58) which is proportional to laser gain, detecting the second control tone (30) from a portion of the light output of the laser as a fourth signal (60) which occurs only if the laser is being modulated in or below the lasing threshold region, and substantively combining the third (58) and fourth (60) signals to generate a fifth signal (84) for use as a control of the amplitude of the NRZ working signal (18).

Abstract: In a multinode switch array, the maximum number of nodes that can be passing data from input to output lead can be no greater than the number of output leads in the array. Thus, the remaining nodes, while not performing a useful switch function, when implemented in CMOS (complementary metal oxide semiconductor), are consuming power due to changing logic levels in the circuitry and are causing the input data drivers to consume power due to the loading effect of the non-functional but actively connected nodes. The present invention overcomes these prior art disadvantages by ascertaining from the indirect address data stored in connect memory of each node, the times that the traffic memory needs to be activated and deactivates the memory and any associated driver at all other times in a manner such that it and the data driver are not consuming power incurred by data transfer operations.

Abstract: In one embodiment, a method of providing phase detection from a circuit having first and second inputs and at least one output is disclosed. The method includes a cyclical operation of four steps. The first step awaits the receipt at the first input of an input signal which at least meets the requirements of one of two given binary values. The second step awaits the receipt at the first input of an input signal which at least meets the requirements of the other of the two given binary values before providing an output signal of a first value at the output. The third step awaits the receipt at the second input of an input signal which at least meets the requirements of one of two given binary values. The fourth step awaits the receipt at the second input of an input signal which at least meets the requirements of the other of the two given binary values before changing the output signal at the output to a second value. The process then returns to the first step.

Abstract: Various optical amplifier configurations are disclosed. In one configuration, an optical amplifier provides an amplified output signal through use of a pumping device. The output signal is split to an output and a feedback input. The feedback signal is converted to a current which is sensed by a controller. The controller adjusts the amount of current to the pumping device in various instances. In one instance, the current is controlled to prevent overdriving the pumping device. In another instance, the current is controlled to maintain the output signal at a substantially constant level. In another configuration, the optical amplifier is coupled to a ratio computation block which measures the operating efficiency of the pumping device. Additional components detect an undesirable efficiency and provide a warning of the same.

Abstract: A method and system for hitlessly rearranging a communications matrix and maintaining connections of previously connected signals forms an immediate and temporary connection configuration of a predetermined input gate to a predetermined output gate through a dedicated center stage switch of the communications matrix. The method and system use a predetermined center stage switch other than the dedicated center stage switch to establish a parallel connection configuration from the predetermined input gate to the predetermined output gate. At the input gates, the parallel connection configuration forms a head-end-bridge. At the output gates, the parallel connection configuration forms a receive-end-switch. Once parallel connections exist through the predetermined center stage switch and the dedicated center stage switch, the connections through the dedicated center stage switch are disconnected to free the dedicated center stage switch.

Abstract: An easily attached and detached locking mechanism is provided to prevent accidental disconnection between mounted and removable connector elements. The mechanism comprises interconnected and tensioned arms with tangs that enclose the connector elements with the interconnection and the tangs providing forces in opposite directions to maintain the connector elements in contact. Inward forces, on the ends of the tensioned arms opposite the tangs, increase the distance between the tangs for attachment of or removal from the connectors to be locked together.

Abstract: A server combines a multiplexer/demultiplexer with a circuit switch to handle both high-speed overhead and data interfaced to the server through a cross-connect; multiple servers may be connected to the cross-connect in a star, mesh or ring network.

Abstract: A subscriber equipment (210) is isolated (238, 234) at a line card (208) in a line shelf (200) and drop testing is conducted over a test-out bus (240) by a test unit (220) connected (236) to the subscriber equipment (210); the test unit (220) may be plugged into any line card slot in any of a plurality of line shelves (200, . . .

Abstract: A self-regulating oscillator circuit and method are disclosed. Specifically, a method is described whereby an oscillator having an active device is operated. The oscillator is operated by providing a current through the active device, as well as through a reference device connected in series with the active device of the oscillator. A reference voltage across the reference device is sampled, and a regulated voltage is generated by adding a predetermined voltage to the sampled reference voltage. Finally, the regulated voltage is applied to the active device of the oscillator. In one circuit embodiment, the oscillator as described includes a gallium arsenide FET structure which cooperates with a resonant structure to produce a reflection-type oscillator. In addition, a regulator circuit is described including an isolating op amp which samples the reference voltage from the active device of the oscillator and provides its output to a voltage source device.

Abstract: All available timeslots for interconnecting a circuit between two endpoints in a telecommunications network are considered for selecting and establishing the path wherein the selecting step may be carried out according to the rule of first feasible timeslot and wherein bandwidth may be determined as being equal to the lowest count among the timeslots determined to be feasible in each network element in a given path and wherein the total bandwidth in the network between two endpoints is determined by adding the bandwidths determined for each possible path.

Abstract: An interdigital capacitor (10) is provided including a plurality of conductive and dielectric finger regions. The conductive finger regions are made of the same material type as a microstrip transmission line (12). The conductive finger regions are comprised of individual conductive fingers (14) and the individual conductive fingers (14) provide a predetermined level of impedance to the microstrip transmission line. The plurality of conductive finger regions are comprised of a first finger region (18) and a second finger region (20). The first finger region (18) is coupled to the microstrip transmission line (12) and the second conductive finger region (20) is coupled to ground (22). The individual conductive fingers (14) of the first conductive region (18) are located parallel and interspersed with the individual conductive fingers (14) of the second conductive finger region (20).

Abstract: A message priority scheme for use in local areas networks (LANS) operating in accordance with carrier sense, multiple access/collision detect (CSMA/CD) bus access protocol. A LAN station having a high priority message to send ignores the carrier sense signal, and thereby obtains immediate bus access. If the high priority message collides with another message already on the bus, both messages are subject to a backoff period. However, the backoff period for a high priority message is guaranteed to be less than that of a low priority message for a certain number of re-transmission attempts. An intermediate priority status is assigned to a message that previously had a high priority status, after a certain number of transmission attempts. The intermediate priority message is deprived of its ability to transmit while ignoring the carrier sense signal, but retains its shorter backoff period.