Patents Assigned to Alpha and Omega Semiconductor Incorporated
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Patent number: 9711631Abstract: An IGBT device includes a substrate having a bottom semiconductor layer of a first conductivity type and an upper semiconductor layer of a second conductivity type, at least one first gate formed in a corresponding first trench disposed over the substrate, and a second gate formed in a second trench disposed over the bottom semiconductor layer. The first and second trenches are provided with gate insulators on each side of the trenches and filled with polysilicon. The second trench extends vertically to depth deeper than the at least one first trench. The IGBT device further includes a body region of the first conductivity type provided between the at least one first gate and/or the second gate, and at least one stacked layer provided between a bottom of the at least one first gate and a top of the upper semiconductor layer. The at least one stacked layer includes a floating body region of the second conductivity type provided on top of a floating body region of the first conductivity type.Type: GrantFiled: March 10, 2016Date of Patent: July 18, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Jun Hu
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Publication number: 20170200705Abstract: A power device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.Type: ApplicationFiled: January 12, 2016Publication date: July 13, 2017Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Xiaotian Zhang, Shekar Mallikarjunaswamy, Zhiqiang Niu, Cheow Khoon Oh, Yueh-Se Ho
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Patent number: 9704955Abstract: Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.Type: GrantFiled: October 19, 2016Date of Patent: July 11, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hamza Yilmaz, Xiaobin Wang, Anup Bhalla, John Chen, Hong Chang
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Patent number: 9705395Abstract: A fault tolerant power supply system includes at least one load switch configured to connect an input voltage to an output node of the load switch when the load switch is turned on and at least one power channel coupled to the load switch to receive the input voltage. The power channel is configured as a buck converter and includes at least a high-side power switch and a low-side power switch. The fault tolerant power supply system is configured to measure a current flowing through the low-side power switch, to determine that the current flowing through the low-side power switch has exceeded a current limit threshold, and to disable the low-side power switch and the load switch in response to the determination that the current flowing in the low-side power switch has exceeded the current limit threshold.Type: GrantFiled: July 7, 2015Date of Patent: July 11, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Mark Tomas, Zhiye Zhang, Allen Chang, Kuang Ming Chang, Gilbert Lee
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Patent number: 9698237Abstract: A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.Type: GrantFiled: March 1, 2016Date of Patent: July 4, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Shekar Mallikarjunaswamy, Francois Hebert
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Patent number: 9697450Abstract: A magnetic stripe data transmission (MST) driver and a method for driving the MST are disclosed. The MST driver is configured to transmit magnetic strip data comprising of streams of pulses. The MST driver comprises a pair of high side switches and a pair of low side switches. The pair of high side switches comprises a first switch and a second switch. The pair of low side switches comprises a third switch and a fourth switch. The first, second, third and fourth switches are arranged in a full bridge type configuration connected across a voltage source and a ground. An inductive coil is connected across outputs of the full bridge type configuration of the switches. The MST driver includes a switch driver configured to drive the pair of low side switches and the pair of high side switches under current slope control using pulse width modulation.Type: GrantFiled: July 29, 2016Date of Patent: July 4, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventor: Gilbert S. Z. Lee
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Patent number: 9691863Abstract: Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: GrantFiled: April 8, 2015Date of Patent: June 27, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Hongyong Xue, Sik Lui, Terence Huang, Ching-Kai Lin, Wenjun Li, Yi Chang Yang, Jowei Dun
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Publication number: 20170179107Abstract: A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.Type: ApplicationFiled: February 28, 2017Publication date: June 22, 2017Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Ning Shi, Lingpeng Guan, Madhur Bobde
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Patent number: 9685443Abstract: An integrated circuit includes an active device formed in a semiconductor layer of a first conductivity type, a first guard ring of the first conductivity type formed in the semiconductor layer surrounding at least part of the active device; a second guard ring of the second conductivity type formed in the semiconductor layer surrounding the first guard ring and the active device and including comprising alternating first well regions of the first conductivity type and the second well regions of the second conductivity type, the first and second well regions being electrically shorted together and electrically coupled to a ground potential or floating; and a third guard ring of the first conductivity type formed in the semiconductor layer surrounding the second guard ring. The first and third guard rings do not receive direct electrical connection.Type: GrantFiled: May 24, 2016Date of Patent: June 20, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Shekar Mallikarjunaswamy
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Patent number: 9684326Abstract: A simple, cost-effective and efficient short circuit protection with simple routing of the ground on the PCB is achieved in an asynchronous DC-DC boost converter wherein a voltage sensing controller selectively isolates an input power supply to a load in the event of a short circuit. The controller alleviates need for additional components by utilizing the circuit for under voltage lockout protection and the circuit for overvoltage protection to generate signals for detecting short circuit. A predetermined offset voltage is added to a sensed output voltage to generate a reference voltage that is compared to a sensed input voltage and an output signal having a high state is generated in the event that the reference voltage is less than the sensed input voltage for selectively disabling the source of input power when the output signal is in the high state.Type: GrantFiled: February 21, 2014Date of Patent: June 20, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventor: Gilbert S. Lee
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Patent number: 9685430Abstract: A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of the second plurality of vias; and electrically connecting the plurality of conductive plugs on the electrodes of the plurality of chips to the plurality of conductive plugs on the plurality of pins.Type: GrantFiled: December 10, 2015Date of Patent: June 20, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Zhiqiang Niu, Hua Pan, Ming-Chen Lu, Yueh-Se Ho, Jun Lu
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Patent number: 9685523Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.Type: GrantFiled: December 17, 2014Date of Patent: June 20, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Madhur Bobde, Harsh Naik, Lingpeng Guan, Anup Bhalla, Sik Lui
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Patent number: 9685435Abstract: Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.Type: GrantFiled: January 4, 2016Date of Patent: June 20, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Sik Lui, Ji Pan
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Patent number: 9679833Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.Type: GrantFiled: September 9, 2016Date of Patent: June 13, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Ming-Chen Lu, Hongtao Gao
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Patent number: 9679822Abstract: A method of monitoring an epitaxial growth geometry shift is disclosed. First, second and third trenches are formed on a semiconductor wafer. An epitaxial layer is grown. The epitaxial layer covers the first trenches and the second trenches but not the third trenches. First and second recesses on a top surface of the epitaxial layer are formed. First and second openings aligned with the first and the second recesses and a third openings aligned with the third trenches are formed in a photoresist layer. A corresponding first offset between a top center and a bottom center of each first recess is measured. An offset value of the top center from the bottom center of said each first recess is determined. A corresponding second offset between a top center of each second recess and a center of corresponding second opening is determined. A corresponding third offset between a center of each third trench and a center of corresponding third opening is measured.Type: GrantFiled: February 22, 2016Date of Patent: June 13, 2017Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Boxiu Cai, Lingbing Chen, Yiming Gu
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Patent number: 9673289Abstract: A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness. In one embodiment, the second thickness is greater than the first thickness. In another embodiment, the trench gate in each of the active trench and the termination trench is formed as a single polysilicon layer.Type: GrantFiled: October 12, 2015Date of Patent: June 6, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Daniel Calafut, Madhur Bobde, Yeeheng Lee, Hong Chang
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Patent number: 9666666Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.Type: GrantFiled: May 14, 2015Date of Patent: May 30, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
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Publication number: 20170148910Abstract: The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.Type: ApplicationFiled: February 6, 2017Publication date: May 25, 2017Applicant: Alpha and Omega Semiconductor IncorporatedInventors: Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
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Patent number: 9653424Abstract: This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.Type: GrantFiled: October 29, 2014Date of Patent: May 16, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Xiaotian Zhang, Jun Lu, Kai Lu
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Patent number: 9647078Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.Type: GrantFiled: August 28, 2015Date of Patent: May 9, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Shekar Mallikararjunaswamy