Patents Assigned to Alpha & Omega Semiconductor (Cayman), Ltd.
  • Patent number: 11196409
    Abstract: A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate the ramp signal with optimal slope compensation built into the ramp signal.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 7, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Nicholas I. Archibald, Rhys S. A. Philbrick, Steven P. Laur
  • Patent number: 11170926
    Abstract: An isolation coupling structure for transmitting a feedback signal between a secondary side and a primary side of a voltage conversion device includes a first dielectric layer including a first face and a second face opposite to the first face, a first coupling coil disposed on the first face enclosing to form an inner region; a second coupling coil configured to couple with the first coupling coil. The second coupling coil includes a first coil portion and a second coil portion, where the first coil portion is disposed on the second face, the second coil portion is disposed on the first face and located inside the inner region. The second coil portion is isolated from the first coupling coil, and the first coil portion and the second coil portion are electrically connected. The technical effect is that it can realize the electrical isolation and the coupling with low cost and small package size.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: November 9, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Jung-Pei Cheng, Hsiang-Chung Chang, Yu-Ming Chen, Chieh-Wen Cheng, Tsung-Han Ou, Lih-Ming Doong
  • Patent number: 11152351
    Abstract: A bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating optimized collector-base junction realizing avalanche mode breakdown. In some embodiments, the bidirectional transient voltage suppressor is constructed as an NPN bipolar transistor incorporating individually optimized collector-base and emitter-base junctions with the optimized junctions being spatially distributed. The optimized collector-base and emitter-base junctions both realize avalanche mode breakdown to improve the breakdown voltage of the transistor. Alternately, a unidirectional transient voltage suppressor is constructed as an NPN bipolar transistor with a PN junction diode connected in parallel in the reverse bias direction to the protected node and incorporating individually optimized collector-base junction of the bipolar transistor and p-n junction of the diode.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: October 19, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 11127520
    Abstract: A voltage converter comprises a second controller as a power switch of the secondary side of the transformer for comparing a detection voltage representing an output voltage and/or load current with a first reference voltage and generating a control signal, and a coupling element for transmitting the control signal generated by the second controller to the first controller on the primary side of the transformer enabling the first controller to generate a first pulse signal driving the power switch to control the on/off state of the primary side winding.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 21, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Tien-Chi Lin, Yu-Ming Chen, Jung-Pei Cheng, Pei-Lun Huang
  • Patent number: 11099589
    Abstract: An error amplifier circuit receives first and second input signals and provides an error amplifier output signal indicative of the difference between the first and second input signals. The error amplifier circuit implements a proportional-integrator-differentiator (PID) circuit having a differential input signal path and including a proportional amplifier circuit, an integrator amplifier circuit, and a differentiator amplifier circuit. The differentiator amplifier circuit receives an AC coupled input signal. The error amplifier circuit sums the output from the proportional amplifier circuit, the integrator amplifier circuit and the differentiator amplifier circuit to provide the error amplifier output signal where the error amplifier output signal is referenced to a first bias voltage.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 24, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Steven P. Laur, Rhys Philbrick, Nicholas Archibald
  • Patent number: 11094617
    Abstract: A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 17, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventor: Yan Xun Xue
  • Publication number: 20210223838
    Abstract: A multi-port power delivery system includes a first universal serial bus (USB) port, a second USB port, a first power conversion unit, a second power conversion unit, a power delivery control circuit and a switch circuit. The first USB port is configured to output power delivered to a first power path. The second USB port is configured to output power delivered to a second power path. The first power conversion unit has a first output terminal coupled to the first power path. The second power conversion unit has a second output terminal coupled to the second power path. The power delivery control circuit generates a switch control signal according to first connection information on the first USB port and second connection information on the second USB port. The switch circuit selectively couples the first output terminal to the second output terminal according to the switch control signal.
    Type: Application
    Filed: January 16, 2020
    Publication date: July 22, 2021
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Pao-Yao Yeh, Yu-Ming Chen, Jung-Pei Cheng, Hsiang-Chung Chang
  • Patent number: 11069604
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: July 20, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD. GRAND
    Inventors: Xiaotian Zhang, Yan Xun Xue, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Patent number: 11069804
    Abstract: A power device, comprising, a semiconductor substrate composition having a substrate layer of a first conductivity type, one or more lateral double diffused metal oxide semiconductor (LDMOS) devices formed in the substrate layer. LDMOS structures are integrated in to the isolation region of a high voltage well. Each LDMOS is isolated from a power device substrate area by an isolator structure formed from the substrate layer. Each LDMOS comprises a continuous field plate formed at least partially on the thick insulation layer over each of the one or more LDMOS devices and in conductive contact with the power device substrate area.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 20, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventor: Vipindas Pala
  • Patent number: 11062969
    Abstract: A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 13, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Cheow Khoon Oh, Ming-Chen Lu, Xiaoming Sui, Bo Chen, Vincent Xue
  • Patent number: 11038022
    Abstract: A superjunction power semiconductor device includes a termination region with superjunction structures having higher breakdown voltage than the breakdown voltage of the active cell region. In one embodiment, the termination region includes superjunction structures having lower column charge as compared to the superjunction structures formed in the active cell region. In other embodiments, a superjunction power semiconductor device incorporating superjunction structures with slanted sidewalls where the grading of the superjunction columns in the termination region is reduced as compared to the column grading in the active cell region. The power semiconductor device is made more robust by ensuring any breakdown occurs in the core region as opposed to the termination region. Furthermore, the manufacturing process window for the power semiconductor device is enhanced to improve the manufacturing yield of the power semiconductor device.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 15, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Publication number: 20210175155
    Abstract: An interconnected base plate comprises a metal layer, a plurality of metal pads, and a molding encapsulation. The mold compound layer encloses a majority portion of the plurality of metal pads 240. A respective top surface of each of the plurality of metal pads is exposed from a top surface of the molding encapsulation. The respective top surface of said each of the first plurality of metal pads and the top surface of the mold compound layer are co-planar. A power module comprises the interconnected base plate, a plurality of chips, a plurality of bonding wires, a plurality of terminals, a plastic case, and a module-level molding encapsulation. A method, for fabricating an interconnected base plate, comprises the steps of forming a plurality of metal pads; loading a metal layer; forming a molding encapsulation; and applying a singulation process.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Zhiqiang Niu, Bum-Seok Suh, Long-Ching Wang, Son Tran, Junho Lee, Yueh-Se Ho
  • Patent number: 11031465
    Abstract: A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile formed in the field stop zone includes varying, non-constant doping levels. In some embodiments, the enhanced doping profile includes one of an extended graded doping profile, a multiple stepped flat doping profile, or a multiple spike doping profile. The epitaxial layer field stop zone of the present invention enables complex field stop zone doping profiles to be used to obtain the desired soft-switching characteristics in the semiconductor device.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 8, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Lei Zhang, Karthik Padmanabhan, Lingpeng Guan, Jian Wang, Lingbing Chen, Wim Aarts, Hongyong Xue, Wenjun Li, Madhur Bobde
  • Patent number: 10991680
    Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 27, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Madhur Bobde, Xiaobin Wang, Lin Chen
  • Patent number: 10969848
    Abstract: A system power monitor circuit and method implemented in a system including multiple power supplies measures and scales the power supply output current value at each power supply as a ratio of the power supply output voltage and a reference voltage. Scaled power supply output current values are combined to provide a single system current signal that is referenced to the same reference voltage value being the system voltage signal. The system power is determined from the system current signal and the system voltage signal. In some embodiment, a power supply output voltage of a selected power supply is used as the reference voltage.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 6, 2021
    Assignee: Alpha & Omega Semiconductor (Cayman) Ltd.
    Inventor: Chris M. Young
  • Patent number: 10958170
    Abstract: A computer program product and DC-to-DC converter comprising, an electronic switching device, an inductor coupled to the electronic switching device, a capacitor coupled to the inductor wherein the inductor and capacitor are chosen such that the resistance of the load line is greater than a gain minus the equivalent series resistance. A transient controller is communicatively coupled to the electronic switching device, wherein the transient controller has adaptive voltage positioning and wherein the transient controller sends a signal configured to initiate discharging the capacitor during a transient event.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 23, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventor: Amir Babazadeh
  • Publication number: 20210082790
    Abstract: A power semiconductor package includes a lead frame, a low side field-effect transistor (FET), a high side FET, a first metal clip, a second metal clip, an inductor assembly, and a molding encapsulation. The low side FET is flipped and is attached to a first die paddle of the lead frame. A method for fabricating a power semiconductor package. The method comprises the steps of providing a lead frame; attaching a low side FET and a high side FET to the lead frame; mounting a first metal clip and a second metal clip; mounting an inductor; forming a molding encapsulation; and applying a singulation process.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Xiaotian Zhang, Mary Jane R. Alin, Bo Chen, David Brian Oraboni, JR., Long-Ching Wang
  • Publication number: 20210083088
    Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Madhur Bobde, Xiaobin Wang, Lin Chen
  • Patent number: 10937780
    Abstract: A bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes and a diode triggered clamp device in some embodiment. In other embodiments, a bidirectional transient voltage suppressor (TVS) circuit for data pins of electronic devices includes two sets of steering diodes with a clamp device merged with a steering diode in each set. The TVS circuit is constructed to realize low capacitance at the protected nodes and improved clamping voltage for robust protection against surge evens. In some embodiments, the TVS circuit realizes low capacitance at the protected nodes by fully or almost completely depleting the P-N junction connected to the protected nodes in the operating voltage range. In this manner, the TVS circuit does not present undesirable parasitic capacitance to the data pins being protected, especially when the data pins are applied in high speed applications.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 2, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Shekar Mallikarjunaswamy, Ning Shi
  • Patent number: 10931276
    Abstract: An apparatus comprising an insulated gate bipolar transistor; and a super-junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor wherein the super-junction metal-oxide semiconductor field effect transistor are structurally coupled and wherein the super-junction metal-oxide semiconductor field effect transistor is configured to switch to an ‘on’ state from an ‘off’ state and an ‘off’ state from an ‘on’ state.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 23, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Bum-Seok Suh, Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan