Abstract: A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto.

Abstract: A computer system employs virtual channels and allocates different resources to the virtual channels. More particularly, the computer system provides a posted commands virtual channel separate from the non-posted commands virtual channel for routing posted and non-posted commands or requests through coherent and noncoherent fabrics within the computer system. Because separate resources are allocated to the virtual channels in the computer system, posted requests may be allowed to become unordered with other requests from the same source. Implementation of a separate posted commands virtual channel may allow the computer system to maintain compatibility with I/O systems in which posted write requests may become unordered with previous posted requests (e.g., the Peripheral Component Interconnect Bus, or PCI). Implementation of the separate posted commands virtual channel thus may assist in providing deadlock-free operation.

Abstract: A voltage-controlled oscillator circuit includes a ring oscillator circuit for generating a signal having a series of pulses. The signal with the series of pulses is ac coupled to a filter circuit which converts the series of pulses into a substantially sinusoidal signal which is substantially symmetrical about the reference potential of the system. The sinusoidal signal is applied to an amplifier which converts the sinusoidal signal into a square wave. Because the square wave is generated as an amplified sine wave, it exhibits a high degree of symmetry, i.e., it has a highly accurate 50-50 duty cycle, which makes it applicable in demanding settings such as serving as a clock signal in a high-speed microprocessor system in which both rising and falling edges of the clock signal are used to synchronize events.

Abstract: A structure and method for mounting a processor assembly on a mother board and a structure and method for cooling the processor assembly are described. The processor assembly includes a processor circuit board assembly which is located adjacent to a heat sink for removing heat from the circuit board assembly. The heat sink and circuit board assembly are maintained in an upright position with respect to the mother board by a frame mounted on the mother board and/or the computer system chassis. A cover mounted to the top of the frame holds a connector on the processor circuit board assembly in mating contact with a connector on the mother board. The cover also serves to complete an enclosure around the heat sink and processor circuit board assembly. Fans mounted to the frame move air from an intake end of the processor assembly, across cooling fins on the heat sink, to an outlet end of the processor assembly such that a ducted cooling system is provided for the processor assembly.