Abstract: Vertical deflection circuitry for substantially eliminating rolling and bouncing in a video monitor, where, for example, the video monitor successively displays images produced by each of one of a plurality of non-synchronized video cameras and an incoming vertical synchronization (synch) signal to the monitor is merely a composite of the individual vertical synch signals generated by each of these cameras. Specifically, the vertical deflection circuitry generates the appropriate vertical sweep signal for a current one of these cameras from this composite synch signal so as to properly locate the corresponding video image generated by this camera on a display screen of the monitor.

Abstract: Circuitry is disclosed which compensates for magnitude and phase variations in the transfer function of a transmission medium. The medium is characterized by amplitude and phase variations in its transfer function wherein the amplitude variations produce increasing loss in the medium as frequency increases. The circuitry possesses an inverse characteristic to these variations, thereby generating a relatively flat magnitude characteristic for the medium-circuitry combination. The circuitry includes a buffer amplifier that receives a portion of an input signal, a network coupled to the amplifier and having zero-pole pairs in its signal transfer function, and a summer which has both the input signal and the output of the network as inputs. Accordingly, the compensation circuit has an overall transfer function which has fixed poles but adjustable zeros, these zeros being dependent on the amplifier gain and the portion of the input signal applied to the amplifier.

Abstract: Circuitry is disclosed for regenerating a digital output stream referenced to an output timing signal from a digital input stream referenced to an input timing signal wherein the input and output timing signals are typically unsynchronized. Both the digital input stream and a delayed version of the input stream alternately serve as inputs to a dual-port memory. The output port of the memory emits the output stream under control of the output timing signal. Whenever the output stream is being transferred from the dual-port memory to an output buffer, the storing of data through the input port of the memory is temporarily suspended. In order to ensure that no input data is lost, the delayed input stream is presented to the memory after interrupt of the memory by the output timing signal. Prior to the interruption, the input port receives its input directly from the input stream. The delay interval is chosen to be commensurate with the output timing signal to preserve data input into the memory.

Abstract: An image processing system, which receives asynchronous analog video output signals from a plurality of independently operating video cameras (preferably four) and simultaneously displays the image obtained from each camera, dimensionally reduced by a factor of two, on a non-overlapping basis on one video monitor, is described.

Abstract: An automatic gain control (AGC) and digitizing circuit, particularly suitable for use in digital video image processing and/or display systems, is disclosed. This circuit advantageously defines an active window within an image area and operates the AGC only on the active window in order to ensure that the active window is always displayed, on a remote monitor, with proper brightness and contrast. The active window can be located anywhere within the image area and can be set to encompass an area extending from only a single picture element to the entire image area.