Abstract: An underfilling method for a flip-chip packaging process includes coating a underfill material layer over bumps on a semiconductor substrate, performing a die sawing process on the semiconductor substrate to from a number of dies, and performing a flip-chip process on each of the dies to adhere each of the dies to another substrate. Because the underfill material is coated from the top of the bumps, the air-trapping problem can be eliminated. The process time is shortened to improve yield because the underfill material is dispensed over all the dies before the die-sawing process. This is different from the conventional underfilling process, which has to dispense underfill material and seal edges on each individual die.

Abstract: A method for burn-in testing a complete wafer comprising the steps of first providing a wafer, and then forming a plurality of bumps thereon. Next, a tape-automated bonding tape having a plurality of bonding pads is designed and fabricated, wherein each bonding pad includes a corresponding circuit and an external contact point. Then, electrical connections between the bonding pads and the bumps are made and a plurality of voltages and currents are supplied through the tape-automated bonding tape for carrying out burn-in tests. Bum-in tests are performed for the whole wafer. Defective chips are singled out after the wafer is cut up and only good chips are used for subsequent packaging. Therefore, production cost can be saved and packaging yield can be increased. Furthermore, a multiple circuit layers design can be employed to fabricate the tape-automated bonding tape. Consequently, circuits necessary for carrying out the burn-in test for the whole wafer is simplified.

Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: An IC package architecture and a method of manufacturing the same are provided. By this packaging method, a molded compound is first formed, which covers the entire packaging area of the leadframe but leaving a window to expose the area where the chip is to be mounted. After the chip is mounted and wire bonded, a dispensed compound is formed the window to enclose the chip therein. The dispensing material can be variably selected by the manufacturer in accordance with actual application requirements. For instance, the dispensing material can be either a transparent material to allow the enclosed chip to be transparent to the outside, or a colored material for some prespecified identification purpose of the IC package. Moreover, the packaging method can be utilized on current types of IC packages and can be realized by using existing equipment and processes in a cost-effective manner without having to invest on new additional ones.

Abstract: A pre-erase/incremented erase mechanism is employed to reduce excessive tunnel oxide fields in flash memory cells. A variable conditioning signal removes charge from “fast” bits in the array, so that they are configured to have threshold voltages closer to an ideal initial state in preparation for an erase cycle. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: A circuit and method for achieving an improved pre-programming of flash memory cells is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for hot electron pre-programming operations. By eliminating the need to pre-program the memory array with hot electrons, the invention provides a signicant improvement for flash arrays, because device life and reliability is extended. In addition, pre-programming time and power is reduced significantly since the operation takes place on a sector (parallel) basis rather than a single bit line (serial) basis, and a charge pump is not needed to generate the current injected into floating gates of cells in the sector.

Abstract: A novel erase mechanism using junction hot hole injection is disclosed for flash memory cell sector and bulk erase operations. A constant current supply is used so that a suitable junction voltage breakdown can be provided despite expected variations in cell structures, operations, etc. The inventive method eliminates the need for dual polarity voltage supplies for erase operations, and provides a method to achieve a tight distribution of erased cell threshold voltages. In addition, over-erasure problems associated with Fowler-Nordheim tunneling are essentially eliminated.

Abstract: A novel cell conditioning mechanism is employed to equalize charge discharge characteristics of flash memory cells. A variable conditioning signal removes charge from "fast" bits in the array, and leaves other cells relatively unaffected so that the fast bits are adjusted to have threshold voltages closer to those of the other cells in an array. In this manner, the voltage thresholds are tightened and equalized, so that over-erasure problems associated with Fowler-Nordheim tunneling erase operations are substantially reduced, and endurance cycles for the array are maximized. The invention can be used in a device in the field, or as part of a design process for a flash memory cell to evaluate device performance.

Abstract: An architecture for a dual-chip IC package and a method of manufacturing the same are provided. The dual-chip IC package allows two chips to be mounted on the same leadframe in the same package. The two chips can be either the same type of a semiconductor device or two different types of semiconductor devices with different functions such as a memory chip and a logic control chip. The architecture allows a simplified manufacturing process and an increased good yield rate for the two IC chips that are to be enclosed in the dual-chip IC package. Moreover, the dual-chip IC package can be manufactured with existing packaging equipment and processes, so that it can be realized without having to invest on and install additional ones.

Abstract: A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Abstract: A circuit and method for achieving compressed distributions of erased cell threshold voltages in an EEPROM array is disclosed. The invention, when used to condition flash memory cell arrays, results in increased endurance of such arrays, and eliminates the need for pre-programming operations before a bulk erase can take place. By eliminating the need to pre-program the memory array before each erasure, the process provides a signicant improvement for low power applications, because battery life is extended and write cycle time is enhanced.

Abstract: A test circuit for observing charge retention characteristics of cells in a flash memory array is disclosed. Unlike prior art structures, the present circuit monitors both charge loss and charge gain of cells in the array. In this way, cells having conduction thresholds below a desired target threshold and cells having conduction thresholds above a desired target threshold can both be observed. The circuit includes a regular memory array, and a mirror array formed with devices having opposite channel types to the regular array. By identifying and evaluating more accurately the threshold characteristics of a particular cell design or cell process, improvements can be made to such designs and processes in a more rapid and optimal fashion.