Abstract: An optical sensor includes an array of pixels, wherein each pixel includes a photodiode configured to receive an optical signal and a floating node coupled to the photodiode. At least one sensing path is capacitively coupled to the floating node of at least one of the pixels. An evaluation unit is coupled to the at least one sensing path to generate an electrical signal dependent on the optical signal received by the photodiode.

Abstract: An image sensor comprises an array comprising rows and columns of pixels, a first number N of connection lines connected to a first number N of pixels of the array, a voltage regulating circuit having an output, a first terminal, and a driver circuit. The driver circuit has a first number N of switches coupled to the first number N of connection lines and to the output of the voltage regulating circuit, and a first number N of further switches coupled to the first number N of connection lines and to the first terminal. The first number N is at least two.

Abstract: A pixel cell includes a pixel set with a plurality of pixels, with each pixel of the pixel set being configured to capture optical information incident upon the respective pixel and generate electrical information representative of the optical information. The pixel cell further includes a readout circuit which is configured to manage collection and output of the electrical information from each pixel of the pixel set and to operate the pixel set in a global shutter mode and in a rolling shutter mode of operation. In the global shutter mode, the electrical information from each pixel is combined for generating a global shutter output signal, while in the rolling shutter mode, the electrical information from each pixel is used to generate individual rolling shutter output signals.

Abstract: A readout circuit for an image sensor having a pixel array with at least one pixel group, in particular pixel column, with a plurality of pixels connected to a group bus comprises a group input for connecting to the group bus and a signal output for connecting to an input of an ADC. The readout circuit further comprises a first and a second reference terminal for receiving a first and a second reference voltage. A sampling bank comprises at least two sample-and-hold elements connected in parallel between the group input and an output of the sampling bank and further comprises a bypass switch connected in parallel to the sample-and-hold elements. A charge store is connected between the output of the sampling bank and the signal output. A first charge switch is connected between the first reference terminal and the signal output, and a second charge switch is connected between the second reference terminal and the output of the sampling bank.

Abstract: A sensor arrangement includes a first, second, third and fourth group of receiving elements for detecting light in the red, green, blue and infrared wavelength range. At least one first sub-arrangement is formed by arranging one receiving element of the first group, two receiving elements of the second group and one receiving element of the third group in a first Bayer-like pattern. At least one second sub-arrangement is formed by arranging two receiving elements of the second group one receiving element of the fourth group and one receiving element of the first or the third group in a second Bayer-like pattern. The at least one first sub-arrangement and the at least one second sub-arrangement are arranged adjacent to each other in a main plane of extension of the sensor arrangement.

Abstract: A pixel structure includes a substrate body having a light entrance surface, a plurality of first photodiodes formed in the substrate body at a first depth with respect to the light entrance surface, and a second photodiode formed in the substrate body at a second depth with respect to the light entrance surface. The first depth corresponds to a photon absorption length in a material of the substrate body at a first wavelength range, and the second depth corresponds to a photon absorption length in the material of the substrate body at a second wavelength range that is different from the first wavelength range.

Abstract: An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit.

Abstract: In an embodiment a pixel arrangement includes at least one photodiode configured to convert electromagnetic radiation into a respective charge signal, a transfer gate between the photodiode and a capacitance for transferring the respective charge signal to the capacitance, a reset gate electrically coupled to the capacitance, the reset gate configured to reset the capacitance, an amplifier electrically connected to the capacitance and configured to generate, based on the respective charge signal and on a sensitivity mode, a respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively, wherein the low sensitivity signal and the high sensitivity signal are based on a common noise level, a first capacitor configured to store the high sensitivity signal, a second capacitor configured to store the low sensitivity signal, a first switch between an output terminal of the amplifier and the first capacitor and a second switch between the output terminal of the amplifier and the

Abstract: The present disclosure relates to a processing arrangement for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement for determining a digital output value from a digital input value based on a linear function and a square root function. The processing arrangement includes a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function. A selector is configured to select, based on a comparison between the digital input value and a threshold value, whether the digital output value is determined by the first calculation block or by the second calculation block.

Abstract: A pixel includes a transfer gate, and a sample structure having a first sample stage and a second sample stage. The transfer gate and the first and the second sample stages are configured to be operated in conjunction with a light source in response to a control signal. The first sample stage is configured to sample a first sample value that depends on radiation incident on the photosensitive element from an object or a scene that is illuminated by the light source emitting light at a first output power, while the second sample stage is configured to sample a second sample value that depends on radiation incident on the photosensitive element from the object or the scene that is illuminated by the light source emitting light at a second output power. The first output power is different, in particular significantly different, from the second output power.

Abstract: An image sensor system has a pixel array with a plurality of pixels, each of the pixels comprising a photodiode, a pixel buffer and a transfer gate coupled between the photodiode and an input of the pixel buffer. A voltage supply block is configured to generate a pixel supply voltage from an input voltage based on a first reference voltage and to provide the pixel supply voltage to the pixel array. A calibration processing block is configured to determine an average pixel signal based on an average of individual pixel signals at outputs of the pixels of the pixel array and to determine a correction value based on the average pixel signal and a reference pixel signal. A correction processing block is configured to determine the first reference voltage based on a combination of a second reference voltage and the correction value.

Abstract: A pixel cell comprises a plurality of pixels, each pixel comprising a photodiode, a readout circuit comprising a first readout component and a second readout component, wherein a first group of the pixels is configured to detect electromagnetic radiation in a first wavelength range, a second group of the pixels is configured to detect electromagnetic radiation in a second wavelength range, the first readout component is connected with the first group of pixels, the second readout component is connected with the second group of pixels, the first wavelength range is different from the second wavelength range, and the second readout component comprises a plurality of storage capacitors, wherein each pixel of the second group of pixels is assigned to at least one of the storage capacitors, or the second readout component comprises a memory element. Furthermore, a method for operating a pixel cell is provided.

Abstract: An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ?2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.

Abstract: An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer ?2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.