Abstract: An apparatus includes a processing unit that divides an overlay buffer into a plurality of macro blocks, draws a graphic primitive object including a plurality of pixels, identifies one of the plurality of macro blocks upon a determination that the plurality of pixels has crossed a boundary of the one of the plurality of macro blocks, and image processes the one of the plurality of macro blocks.

Abstract: A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF?. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF?, can be used to provide any common mode charge to the input capacitors.

Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.

Abstract: Apparatus and methods for synchronization of multiple semiconductor dies are provided herein. In certain implementations, a reference clock signal is distributed to two or more semiconductor dies that each include at least one data converter. The two or more dies include a master die that generates a data converter synchronization signal, and at least one slave die that processes the data converter synchronization signal to align timing of data conversion operations across the dies, for instance, to obtain a high degree of timing coherence for digital sampling. In certain implementations, the dies correspond to radar chips of a radar system, and the data converter synchronization signal corresponds to an analog-to-digital converter (ADC) synchronization signal. Additionally, the master radar chip generates a ramp synchronization signal to synchronize transmission sequencing across the radar chips and/or to provide phase alignment of ADC clock signals.

Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.

Abstract: Methods, systems and circuits for controlling the power available to the load, by reducing the power available to the load, and additionally or alternatively, limiting the current available by pre-establishing a maximum reference current. The reference current is compared to the actual or estimated current drawn by the load or part of the load. The comparison result is used to control a device or switch which disconnects the power supply or power supply regulator, whether connected directly to the load or connected via voltage dropping device, to one or more or a plurality of the load blocks when the maximum current is exceeded.

Abstract: Radio frequency (RF) isolators are described, coupling circuit domains operating at different voltages. The RF isolator may include a transmitter which emits a directional signal toward a receiver. Layers of materials having different dielectric constants may be arranged to confine the emission along a path to the receiver. The emitter may be an antenna having an aperture facing the receiver.

Abstract: A dither is an uncorrelated signal, usually pseudo-random noise injected into the input of an ADC such that a given input value of the wanted signal becomes spread over a plurality of codes. This reduces the effect of DNL and also smooths the integral non-linearity (INL) response of the ADC. The advantages of introducing dither could be obtained without having to perturb the signal input to the ADC. This avoids the introduction of additional components in the ADC. The dither can be applied to the components used to form a residue of the ADC stage within a pipelined converter. For example, a dither can be applied solely to a DAC part or different dithers can be applied to a ADC and DAC parts respectively. This allows greater flexibility of linearization of the ADC response and the formation of an analog residue by the DAC.

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for eye gaze tracking. In embodiments, a projective surface, such as a virtual reality display screen or augmented reality projective surface, can project light towards a wearer's eyes. The light can be light representing the shape of the projective surface or can be a displayed shape. The light can be reflected from a cornea. The reflected light from the cornea can be received. A distortion of the shape of the projective surface or displayed shape can be used to determine an eye gaze position.

Abstract: RF communication systems that provide combined demodulation and despreading are provided herein. In certain embodiments, an RF communication system generates an in-phase (I) signal and a quadrature-phase (Q) signal based on processing a received spread spectrum signal carrying a sequence of data symbols. The data symbols each have a symbol period and are coded by one or more multi-bit spreading codes. The RF communication system includes a symbol correlator that delays the I signal and the Q signal by an integer number of symbol periods to thereby generate a delayed I signal and a delayed Q signal, respectively. Additionally, the symbol correlator generates a correlation signal based on correlating the delayed I signal to the I signal and correlating the delayed Q signal to the Q signal. The RF communication system processes the correlation signal to recover the sequence of data symbols.

Abstract: Many processes for audio signal processing can benefit from voice activity detection, which aims to detect the presence of speech as opposed to silence or noise. The present disclosure describes, among other things, leveraging energy-based features of voice and insights on first and second formant frequencies of vowels to provide a low-complexity and low-power voice activity detector. A pair of two channels is provided whereby each channel is configured to detect voice activity in respective frequency bands of interest. Simultaneous activity detected in both channels can be a sufficient condition for determining that voice is present. More channels or pairs of channels can be used to detect different types of voices to improve detection and/or to detect voices present in different audio streams.

Abstract: Embodiments of the present disclosure provide an optical range finder that includes a transimpedance amplifier (TIA) and a photodiode emulation circuitry for testing the TIA. The photodiode emulation circuitry may be coupled to an input port of the TIA and configured to receive one or more parameters specifying one or more characteristics of a test current signal to be provided to the TIA. The photodiode emulation circuitry may further be configured to provide the test current signal in accordance with the one or more parameters to the input port of the TIA while the photodiode is also coupled to the input port of the TIA.

Abstract: Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).

Abstract: It is often desirable to distinguish between an open circuit condition and a no signal condition. In both cases an input signal may be absent, but only one of these events represents a failure of the equipment. The present disclosure provides a way to use a difference amplifier to check for open circuit events, without requiring additional circuitry at the input of the amplifier.

Abstract: A calibration apparatus for calibrating a magnetic sensor configured to generate an output signal indicative of magnetic field strength when a bias signal is applied to it is disclosed. The apparatus includes a test magnetic field generator (MFG) to generate magnetic fields of known magnitude, and further includes a processor to control the MFG to generate a known magnetic field, control the sensor to generate a test output signal when the MFG generates the known magnetic field and a known bias signal is applied to the sensor, and determine how to change the bias signal based on a deviation of the measured test output signal from an expected output signal. Using a test MFG that produces known magnetic fields when known bias signals are applied to sensors allows evaluating and compensating for changes in sensitivity of the sensors by accordingly changing bias signals applied to the sensors.

Abstract: Methods, systems and circuits for controlling the power available to the load, by reducing the power available to the load, and additionally or alternatively, limiting the current available by pre-establishing a maximum reference current. The reference current is compared to the actual or estimated current drawn by the load or part of the load. The comparison result is used to control a device or switch which disconnects the power supply or power supply regulator, whether connected directly to the load or connected via voltage dropping device, to one or more or a plurality of the load blocks when the maximum current is exceeded.

Abstract: A charge pump circuit comprises a first charge transfer circuit path coupled including a first boost capacitor coupled to a first clock input, a first charge switch coupled to a circuit input, and a first discharge switch coupled to a circuit output; a second charge transfer circuit path including a second boost capacitor coupled to a second clock input, a second charge switch coupled to the circuit input, and a second discharge switch coupled to the circuit output; a first charge control circuit including a first gate switch coupled to a gate input of the first charge switch, and a first gate-drive capacitor coupled to the gate input of the second charge switch; and a second charge control circuit including a second gate switch coupled to a gate input of the second charge switch, and a second gate-drive capacitor coupled to the gate input of the first charge switch.

Abstract: Disclosed herein are systems and methods for performing DC offset correction of a video signal received over an AC-coupled video link. In one aspect, a transmitter is configured to compute, and provide to a receiver, metadata indicative of a statistical characteristic (e.g., an average or a sum of values) for a group of active pixels of a video signal acquired by a camera. The receiver is configured to compute an analogous statistical characteristic on the video signal received over an AC-coupled video link, and to perform DC offset correction by modifying one or more values of the received video signal based on a comparison of the statistical characteristic computed by the receiver and the one computed by the transmitter and indicated by the received metadata.

Abstract: Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.

Abstract: Various examples are directed to a variable speed comparator circuit comprising a first comparator, a second comparator, and a third comparator and a logic circuit. The first comparator may be configured to generate a first comparator output using a first input and a second input. The second comparator may be configured to generate a second comparator output using the first input and the second input. The third comparator may be configured to generate a third comparator output using the first input and the second input. A propagation delay of the second comparator may be less than a propagation delay of the first comparator. Also, a propagation delay of the third comparator may be less than the propagation delay of the second comparator. The second comparator may have an input offset relative to the third comparator.