Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Abstract: A method for applying optical proximity correction (OPC) to a circuit layout, includes storing distinct defect patterns in a defect pattern library and modifying the circuit layout to fix defect pattern. The method also includes storing a distinct patterns in an OPC pattern library storing one or more post-OPC targets in association with one of distinct patterns in the OPC pattern library, wherein the one or more post-OPC targets are configured to correct optical proximity effects of the associated distinct pattern. The method further includes identifying in the circuit layout a pattern that has substantially the same optical proximity environment as the one of the distinct patterns in the OPC pattern library; and applying OPC to the identified pattern using the one or more post-OPC targets associated with the one of the distinct pattern in the OPC pattern library.

Abstract: A method of inspecting full-chip mask data to locate layout pattern design induced defects and weak points that cause functional failure or performance degradation for integrated circuits (ICs) manufactured in subwavelength technology. Given the pre-OPC integrated circuit design layout data, the method of present invention refers to available post-OPC data or generates post-OPC data condition to do the inspection based on the modeling of integrated circuit wafer patterning. Build-in direct checks of specified electrical functional defects and a multilayer pattern-centric approach are used to improve the accuracy and performance. A technique of adaptive search is used to speed up the critical dimension search during the process of optical proximity correction data verification. A defect synthesis capability is supplied for defect disposition to facilitate systematic correction and prevention of the defects in integrated circuit layout design.