Abstract: An Exclusive-Or circuit has a symmetrical arrangement of components in order to provide an identical input impedance for both input signals and to provide identical switching and signal propagation times. The circuit includes input stages (EF.sub.1, EF.sub.2 ; EF.sub.3, EF.sub.4) for receiving first and second input signals (V.sub.E1 ; V.sub.E2) and emitter followers (EF.sub.5, EF.sub.6, EF.sub.7, EF.sub.8) connected to the input stages. A current switch stage (T.sub.11, T.sub.12, T.sub.13, T.sub.14) is driven by the input stage for the first input signal, and an identical current switch stage (T.sub.21, T.sub.22, T.sub.23, T.sub.24) is driven by the input stage for the second input signal. These current switch stages are connected by load resistors (R.sub.1, R.sub.1) to one pole of an operating voltage source (U.sub.B). Another current switch stage (T.sub.15, T.sub.16), is connected between a current source (I.sub.O /2) and the current switch stage (T.sub.11, T.sub.12, T.sub.13, T.sub.

Abstract: A method of expanding a regular three-stage switching array. Original switching blocks of the first and third stages having a smaller number of crosspoints are enlarged to switching blocks having a larger number of crosspoints, by combining the original switching blocks. In addition, the three stages are expanded by adding additional switching blocks. After the enlarged blocks are formed, at least one additional block is added to the second stage, and some of the connection paths between the enlarged blocks and the blocks of the second stage are rerouted to the additional blocks. The rerouting is performed for the original blocks of the second stage one at a time. In order to avoid disruption of operations during the expansion, while the rerouting is being performed for any particular original block of the second stage, the connections between that original block and the enlarged blocks which would otherwise be established, are switched through redundant connection paths in the second stage.

Abstract: Method and apparatus for output current limitation of a push-pull d.c. voltage converter. The input current of the push-pull d.c. voltage converter is detected and integrated each switching cycle of push-pull switches in the current paths leading to the transformer of the converter. The integrated signal together with a reference signal are utilized to form a control signal for a pulse frequency modulator, the output of which controls the on-periods of the push-pull switches. The arithmetic mean of the output current of the push-pull d.c. voltage converter is thereby kept constant without additional power elements. Operation with a boost-type switch controller as a pre-regulator becomes possible without problems.

Abstract: A ferrite tuning arrangement for a resonator includes a ferrite loaded line in the form of a stripline having an inner conductor, an outer conductor and a ferrite disposed between the inner and outer conductors, with the stripline being adapted for coupling to the resonator. A reflecting termination is provided for the stripline and a magnetic circuit is provided for generating a variable premagnetization field for the ferrite in an orientation perpendicular to a high frequency magnetic field existing in the stripline.

Abstract: A non-recursive half-band filter having a filter length N includes a receiver unit for receiving a complex input signal having a real component and an imaginary component at a sampling frequency fA, where fA=1/T; and a processing and converting unit for processing and converting the received complex input signal into a complex output signal without changing the sampling frequency of the complex input signal. The processing and converting unit operate according to a function of h(l) and the equation: ##EQU1## and includes a modulating unit that modulates a pulse response h(l), where l=-(N-1)/2 to (N-1)/2 and is an odd filter length. As a result of this structure, it is possible to convert a complex input signal s.sub.r1 (kT)+js.sub.i1 (kT) into a complex output signal s(kT)=s.sub.r (k)+js.sub.i (k) by modulating its pulse reponse onto a complex carrier of a frequency equal to 1/4 or 3/4 of the sampling frequency fA, where the null phase of this frequency is an integer multiple of .pi./2 and is kept constant.

Abstract: The invention relates to a timing error detector for clock pulse synchronization in a receiver for synchronous data transmission. The timing error detector receives, as the demodulated received signal, the in-phase component and the quadrature component from the product of the received signal with the output signal of the carrier oscillator, with these components being lowpass filtered so that the signal terms of the double frequency are suppressed. The output signal serves as control signal u.sub.TI for the clock pulse generator. The timing error detector includes two bandpass filters fed with the demodulated received signal and a linkage circuit which generates the control signal from the complex bandpass output signals. The detector is characterized in that a further linkage circuit VF is provided which generates a control signal u.sub.f to control the frequency of the carrier oscillator from the complex output values of bandpass filters BP+ (FIG. 4).

Abstract: A method and apparatus for editing a high-convolutional code for transmisison and its reconversion at a receiver using code puncturing n-output bit streams of a convolutional encoder. The device includes parallel switched data rearrangers at the transmitter provided with control switching circuits which evenly distribute bit streams to the transmission channels. At the receiver, a de-puncturer processes all transmission channels in parallel, downstream of which dummy bits are inserted by a multiplexer and a convolutional decoder subsequently decodes the received data.

Abstract: A light waveguide such as a monomode fiber is inserted into a bore in a body of ductile material, and is mounted and centered using a deformation punch having individual needles which can be moved independently of one another. This provides an improvement over a conventional technique, in which an annular punch is initially employed to exert pressure on the end face of a core member symmetrical to the axis of a sleeve having the core member. For adjustment in accordance with the conventional technique, an asymmetrical pressure is exerted onto the end face in a further process step, with individual punches serving as deformation tools.

Abstract: A method and apparatus of generating a clock pulse signal, which is shifted by any desired, settable phase value between 0 and -.pi. by using two conventional phase shifters which can be set continuously between 0 and -.pi./2, wherein the two input ports of the first phase shifter are fed with the non-delayed frequency-halved signal and with the frequency-halved signal shifted in phase by -.pi./2, respectively, and the two input ports of the second phase shifter are fed with the frequency-halved signal shifted in phase by -.pi./2 and -.pi., respectively. Both phase shifters are actuated jointly, and subsequently the frequency of the thus phase shifted output signals being doubled again. The output or input signals or both of them of the two controllable phase shifters are each filtered through lowpass filters in such a manner that possibly existing harmonics are attenuated in amplitude relative to the frequency-halved signal whereby dynamic behavior and frequency behavior are improved considerably.

Abstract: A mounting and connection system for electrical communications equipment of the type including a plurality of plug-in modules which are each provided with electrical components and with multi-pin connectors, and which are inserted from the front into a magazine whose rear face is provided with a rear wall circuit board. This circuit board, in turn, is provided with multi-socket connectors into which the pin connectors engage. For signals which are to be supplied to all plug-in modules, bus bars are provided with such a bus bar being composed of a plurality of bus bar sections, each formed of a conductor path on the rear wall circuit board and each connecting only one contact socket of two adjacent socket connectors.

Abstract: A switching regulator including a direct voltage source for producing an input voltage, an electronic switch connected between the voltage source and an output for switching the input voltage to the output, a pulse width modulator connected for controlling the electronic switch, a sawtooth signal generator connected for feeding the pulse width modulator a sawtooth signal of constant maximum amplitude, and a proportional signal circuit connected for feeding the pulse width modulator a signal proportional to current through the electronic switch.

Abstract: A regulator controls the DC current flowing through a load, where the current is initially supplied by an AC voltage source and thereafter rectified, the control being proportional to the load current. In one embodiment, the source or emitter potential of a transistor which functions as a control element is changed by a current source such that a current of predetermined strength flows through the control element transistor. The control current for the current source is derived from a current sensor in the load circuit. Additionally, a constant gate potential for the transistor control element is obtained through the current sensor. This circuit is preferably suitable for the regulation of the cathode current of travelling-wave tubes.

Abstract: A switching regulator which substantially suppresses effects on the output voltage of noise in a direct input voltage includes a direct voltage source for producing an input voltage, and output, and a controllable electronic switch connected between the voltage source and the output, an inductance connected between the voltage source and the switch, a pulse with modulator for controlling the switch, a first saw tooth signal producing device for supplying to the pulse width modulator a saw tooth signal, and a device for producing a current proportional voltage which is proportional to current through the inductance. This current proportional voltage is supplied to the pulse width modulator.

Abstract: A bus coupling circuit couples data between a transmitting subscriber and a receiving subscriber using a data transfer bus. Each subscriber includes a bidirectional driver for transmitting and receiving data. Each bidirectional driver includes an apparatus for reintroducing a direct voltage at the bus-sided input of each driver, and a direct voltage splitting device connected between the driver and the bus. Each driver has an input/output port. A hysteresis circuit is connected to each driver and includes a voltage divider disposed between the an input of the driver and a source of supply voltage.

Abstract: A three-stage non-blocking switching array having twice the number of inputs and outputs for its sub-arrays of its input and output stages as the number of lines to be switched, and having one more sub-array in its intermediate stage than the minumum required to form a non-blocking switching array. The additional or redundant inputs and outputs are connected with the non-redundant inputs and outputs such that the redundant inputs are each individually connected with a non-redundant input of a respective other sub-array of the same respective stage. This construction maintains the non-blocking characteristic of the switching array even if one of the sub-arrays fails since, in such use, redundant substitute paths are available.

Abstract: A method of creating an access to a waveguide arrangement in order to couple measuring signals into and/or out of the waveguide arrangement includes providing a cover for covering an opening in a waveguide wall of the waveguide arrangement at a location suitable as a measuring signal access, removing the cover, and replacing the cover with another cover equipped with a coupling device.

Abstract: A method and arrangement for suppressing noise having an alternating voltage component in a load supplied with a direct voltage signal by way of a control loop including a final controller connected to the load. The final controller is connected to the load by way of only an ohmic resistor. The signal at the output of the final controller contains an alternating voltage component of the noise. A signal proportional to the alternating voltage component of the noise in the load is formed in a branch circuit separate from the control loop supplying the load. The proportional signal is fed in phase opposition to the signal appearing at the output of the final controller ahead of the ohmic resistor with an amplitude corresponding to the amplitude of the alternating voltage component of the noise dropped across the ohmic resistor.

Abstract: In a line interface circuit for binary data signals means are provided for compensating varying lengths of line in the receiving and/or transmission path. The output signal of a line equalizer controls a variable impedance circuit in such a way that attenuation of a line build out network is reduced if the output level of the line equalizer falls below a threshold. A transmit line build out network provides a frequency dependent attenuation of binary data by means of a control circuit, which supplies discrete attenuation values according to a logic word.

Abstract: A nonrecursive half-band filter which permits the conversion of a complex-value input signal into a complex-value output signal. The pulse response of the filter is modulated onto a complex carrier at a frequency of 1/4 or 3/4 of the sampling rate, the zero phase of this frequency is a whole multiple of .pi./2, and the sampling rate is halved. Another embodiment of the filter also permits the conversion of a complex-value input signal into a complex-value output signal. In the second embodiment the pulse response is modulated onto a complex carrier of a frequency of one-half the input sampling rate, the zero phase of this frequency is a whole number multiple of .pi./2, and the sampling rate is doubled.

Abstract: A method and a system for processing a data stream for transmission. In order to process the data stream for transmission, particularly for satellite transmission, data substreams are formed and then difference coded and convolutionally coded. After the data substreams are coded, they are combined into phase components in such a manner that all phase components contain convolutionally coded data from each data substream. The convolutional decoding of each data substream again utilizes all phase components.