Patents Assigned to Aplus Flash Technology, Inc.
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Patent number: 6788611Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.Type: GrantFiled: April 25, 2003Date of Patent: September 7, 2004Assignee: Aplus Flash Technology, Inc.Inventors: Fu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
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Publication number: 20040165459Abstract: In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.Type: ApplicationFiled: March 1, 2004Publication date: August 26, 2004Applicant: APLUS FLASH TECHNOLOGY, INC.Inventors: Peter W. Lee, Hung-Sheng Chen, Vei-Han Chan
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Publication number: 20040166634Abstract: In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.Type: ApplicationFiled: March 1, 2004Publication date: August 26, 2004Applicant: APLUS FLASH TECHNOLOGY, INC.Inventors: Peter W. Lee, Hung-Sheng Chen, Vei-Han Chan
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Patent number: 6777292Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.Type: GrantFiled: July 25, 2003Date of Patent: August 17, 2004Assignee: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong
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Patent number: 6757196Abstract: The present invention describes a two transistor flash EEPROM memory cell which has a symmetrical source and drain structure, which permits the cell size not limited by program and erase operations. The memory cell comprises an NMOS floating gate transistor forming a nonvolatile storage device and an NMOS transistor forming an access device. The floating gate transistor is programmed and erased using Fowler-Nordheim channel tunneling. The two transistor memory cell is used in a memory array of columns and rows where a column of cells is coupled by a bit line and a source line, and where a row of cells is coupled by a word line and an access line. The memory array is highly scalable and is targeted for low-voltage, high-speed and high-density programmable logic devices.Type: GrantFiled: December 14, 2001Date of Patent: June 29, 2004Assignee: Aplus Flash Technology, Inc.Inventors: Hsing-Ya Tsao, Peter W. Lee, Fu-Chang Hsu
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Patent number: 6717846Abstract: In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.Type: GrantFiled: October 26, 2000Date of Patent: April 6, 2004Assignee: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Hung-Sheng Chen, Vei-Han Chan
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Patent number: 6714457Abstract: In the present invention programming a plurality of MLC flash memory cells is done in parallel using a channel programming operation by applying a high positive voltage to a word line and positive voltages to the bit lines connected to cells to be programmed. The positive bit line voltages combined with the word line voltage create a channel voltage that is sufficient to program a required Vt level into each cell in parallel during a predetermined amount of time. Using a high positive word line voltage turns on the channel of a cell being programmed and eliminates potential breakdown condition, band to band tunneling current, channel pinch through and hole injection into the gate insulator, while allowing a small symmetrical cell that has low power consumption and a higher endurance cycle.Type: GrantFiled: September 3, 2002Date of Patent: March 30, 2004Assignee: Aplus Flash Technology, Inc.Inventors: Fu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
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Publication number: 20040047203Abstract: A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.Type: ApplicationFiled: January 24, 2003Publication date: March 11, 2004Applicant: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
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Publication number: 20040027856Abstract: A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.Type: ApplicationFiled: January 24, 2003Publication date: February 12, 2004Applicant: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Fu-Chang Hsu, Hsing-Ya Tsao, Han-Rei Ma
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Publication number: 20040027894Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.Type: ApplicationFiled: July 25, 2003Publication date: February 12, 2004Applicant: APLUS FLASH TECHNOLOGY, INC.Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong
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Publication number: 20040029335Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.Type: ApplicationFiled: July 25, 2003Publication date: February 12, 2004Applicant: APLUS FLASH TECHNOLOGY, INC.Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong
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Patent number: 6687154Abstract: A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.Type: GrantFiled: February 11, 2003Date of Patent: February 3, 2004Assignee: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Fu-Chang Hsu
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Publication number: 20040008561Abstract: In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.Type: ApplicationFiled: July 10, 2003Publication date: January 15, 2004Applicant: APLUS FLASH TECHNOLOGY, INC.Inventors: Peter W. Lee, Hsing-Ya Tsao, Vei-Han Chan, Hung-Sheng Chen, Fu-Chang Hsu
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Patent number: 6660585Abstract: In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.Type: GrantFiled: March 21, 2000Date of Patent: December 9, 2003Assignee: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Hsing-Ya Tsao, Vei-Han Chan, Hung-Sheng Chen, Fu-Chang Hsu
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Publication number: 20030206455Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.Type: ApplicationFiled: April 25, 2003Publication date: November 6, 2003Applicant: APLUS FLASH TECHNOLOGY, INC.Inventors: Fu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
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Publication number: 20030206456Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.Type: ApplicationFiled: April 25, 2003Publication date: November 6, 2003Applicant: APLUS FLASH TECHNOLOGY, INC.Inventors: Fu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
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Patent number: 6628563Abstract: A non-volatile integrated circuit memory having an AND-like array structure that is capable of simultaneous reading and writing of digital data to multiple memory cells within the integrated circuit memory has memory cells within an array block of memory cells are arranged in columns and rows. A plurality of block bit lines is in communication with each array block of memory cells such that each block bit line interconnects the memory cells of one column of memory cells within one array block. A plurality of word lines is in communication with each array block of memory cells such that each word line interconnects the memory cells of one row within one array block. The integrated circuit memory further includes a plurality of global bit lines in communication with the array blocks to select a column of the array blocks and to transfer the digital data from and to the array blocks. A bit line selector selectively connects the plurality of global bit lines to the block bit lines.Type: GrantFiled: July 9, 2002Date of Patent: September 30, 2003Assignee: Aplus Flash Technology, Inc.Inventors: Fu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao
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Patent number: 6620682Abstract: In the present invention a method is shown that uses three concurrent word line voltages in memory cell operations of an a NOR type EEPROM flash memory array. A first concurrent word line voltage controls the operation on a selected word line within a selected memory block. The second concurrent word line voltage inhibits cells on non selected word lines in the selected memory block, and the third concurrent word line voltage inhibits non-selected cells in non-selected blocks from disturb conditions. In addition the three consecutive word line voltages allow a block to be erased, pages within the block to be verified as erased, and pages within the block to be inhibited from further erasure. The three consecutive voltages also allow for the detection of over erasure of cells, correction on a page basis, and verification that the threshold voltage of the corrected cells are above an over erase value but below an erased value.Type: GrantFiled: October 16, 2001Date of Patent: September 16, 2003Assignee: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong
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Publication number: 20030161184Abstract: A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.Type: ApplicationFiled: February 11, 2003Publication date: August 28, 2003Applicant: Aplus Flash Technology, Inc.Inventors: Peter W. Lee, Fu-Chang Hsu
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Patent number: 6584034Abstract: In the present invention is disclosed a flash memory for simultaneous read and write operations. The memory is partitioned into a plurality of sectors each of which have a sector decoder. The sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector A 21 decoder is used to demonstrate the invention although other decoders including a 2M decoder and a hierarchical type decoder can be used. The memory array can be configured from a variety of architectures, including NOR, OR, NAND, AND, Dual-String and DINOR. The memory cells can be formed from a variety of array structures including ETOX, FLOTOX, EPROM, EEPROM, Split-Gate, and PMOS.Type: GrantFiled: April 23, 2002Date of Patent: June 24, 2003Assignee: Aplus Flash Technology Inc.Inventors: Fu-Chang Hsu, Peter W. Lee, Hsing-Ya Tsao