Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.

Abstract: A ferroelectric capacitor or a ferroelectric transistor may include a first metal layer having a first metal having a first work function, and a second metal layer having a second metal having a second work function. The capacitor may also include a a vertical electrode and a ferroelectric material that surrounds the vertical electrode and forms a plurality of switching regions in the ferroelectric material. The transistor may include a vertical channel, a vertical buffer layer that surround the vertical channel, and a ferroelectric material that surrounds the vertical buffer layer and forms a plurality of gate regions in the ferroelectric material.

Abstract: A light-emitting diode display including a substrate having a driving circuitry and a plurality of light emitting diode structures disposed on the substrate. Each light-emitting diode structure has a light emitting diode with a light emission zone having a planar portion, and a pigmentless light extraction layer of a UV-cured ink disposed over the light-emitting diode. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion, and the index of refraction of the light extraction layer decreases with distance from the planar portion.

Abstract: Disclosed herein are approaches for forming contacts in a 4F2 vertical dynamic random-access memory device. One method includes providing a plurality of fins extending from a substrate, forming a spacer layer over the plurality of fins, and etching the substrate to expose a base portion of the plurality of fins. The method may include forming a doped layer along the base portion of the plurality of fins and along an upper surface of the substrate, and forming an oxide spacer over the doped layer.

Abstract: Exemplary methods of etching a silicon-containing material may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may include flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber. The methods may include forming a plasma within the remote plasma region to generate plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor. The methods may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The methods may include isotropically etching the layers of silicon nitride while substantially maintaining the silicon oxide.

Abstract: Exemplary methods of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting a remaining silicon-containing material with the carbon-containing precursor. The contacting with the carbon-containing precursor may replenish carbon in the silicon-containing material. The methods may include providing a cleaning agent to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the cleaning agent. The contacting with the cleaning precursor may remove surface oxide from the substrate.

Abstract: Embodiments herein generally relate to polishing pads and methods of forming polishing pads. A polishing pad includes a plurality of polishing elements and a plurality of grooves disposed between the polishing elements. Each polishing element includes a plurality of individual posts. Each post includes an individual surface that forms a portion of a polishing surface of the polishing pad and one or more sidewalls extending downwardly from the individual surface. The sidewalls of the plurality of individual posts define a plurality of pores disposed between the posts.

Abstract: A chemical mechanical polishing system includes a platen to hold a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, and a controller. The polishing pad has a polishing control groove. The carrier is laterally movable by a first actuator across the polishing pad and rotatable by a second actuator. The controller synchronizes lateral oscillation of the carrier head with rotation of the carrier head such that over a plurality of successive oscillations of the carrier head such that when a first angular swath of an edge portion of the substrate is at an azimuthal angular position about an axis of rotation of the carrier head the first angular swath overlies the polishing surface and when a second angular swath of the edge portion of the substrate is at the azimuthal angular position the second angular swath overlies the polishing control groove.

Abstract: A processing chamber may include a gas distribution member, a substrate support, and a pumping liner. The gas distribution member and the substrate support may at least in part define a processing volume. The pumping liner may define an internal volume in fluid communication with the processing volume via a plurality of apertures of the pumping liner circumferentially disposed about the processing volume. The processing chamber may further include a flow control mechanism operable to direct fluid flow from the internal volume of the pumping liner into the processing volume via a subset of the plurality of apertures of the pumping liner during fluid distribution into the processing volume from the gas distribution member.

Abstract: Electrostatic chucks (ESCs) for plasma processing chambers, and methods of fabricating ESCs, are described. In an example, a substrate support assembly includes a ceramic top plate having a top surface with a processing region. One or more electrodes is within the ceramic top plate. A plurality of mesas is within the processing region and on the top surface of the ceramic plate or vertically over an edge of one of the one or more electrodes.

Abstract: A method for recovering ashing rate in a plasma processing chamber includes positioning a substrate in a processing volume of a processing chamber, wherein the substrate has a silicon chloride residue formed thereon. The method further includes evaporating the silicon chloride residue from the substrate. The method further includes depositing the evaporated silicon chloride on one or more interior surfaces in the processing volume. The method further includes exposing the deposited silicon chloride to an oxidizing environment to convert the deposited silicon chloride to a silicon oxide passivation layer. The oxidizing environment can comprise an oxygen-containing plasma, oxygen radicals, or a combination thereof.

Abstract: Embodiments of substrate supports and process chambers equipped with the same are provided. In some embodiments, a substrate support includes: a support body having a first surface; one or more receptacles extending through the first surface and into the support body; and one or more protrusions respectively disposed within corresponding ones of the one or more receptacles and projecting from the first surface, wherein the one or more protrusions at least partially define a substantially planar support surface above the first surface. Methods of eliminating backside wafer damage are also disclosed.

Abstract: Exemplary semiconductor processing chambers may include a substrate support including a top surface. A peripheral edge region of the top surface may be recessed relative to a medial region of the top surface. The chambers may include a pumping liner disposed about an exterior surface of the substrate support. The chambers may include a liner disposed between the substrate support and the pumping liner. The liner may be spaced apart from the exterior surface to define a purge lumen between the liner and the substrate support. The chambers may include an edge ring seated on the peripheral edge region. The edge ring may extend beyond a peripheral edge of the substrate support and above a portion of the liner. A gap may be formed between a bottom surface of the edge ring and a top surface of the liner. The gap and the purge lumen may be fluidly coupled.

Abstract: Described are isolation valves, and chamber systems incorporating and methods of using the isolation valves. In some embodiments, an isolation valve may include a valve body and a flapper assembly. The valve body may define a first fluid volume, a second fluid volume, and a seating surface. The flapper assembly may include a flapper disposed inside the valve body having a flapper surface complimentary to the seating surface. The flapper may be pivotable within the valve body to a first position such that the flapper surface may be away from the seating surface to allow fluid flow between the first fluid volume and the second fluid volume. The flapper may be pivotable within the valve body to a second position such that the flapper surface may be proximate the seating surface to form a non-contact seal to restrict fluid flow between the first fluid volume and the second fluid volume.

Abstract: A method of detecting failure causes in semiconductor processing systems may include receiving an indication of a failure in a semiconductor processing system and providing the indication of the failure as a query to a network representing the semiconductor processing system. The network may include nodes representing on-wafer effects and component functions, and relationships between the nodes that represent causal dependencies between the component functions and the on-wafer effects. The method may also include calculating a change in probabilities assigned to nodes representing the component functions resulting from the query, and generating an output indicating a probability of at least one of the component functions as a cause of the failure.

Abstract: Provided is a processing chamber configured to contain a semiconductor substrate in a processing region of the chamber. The processing chamber includes a remote plasma unit and a direct plasma unit, wherein one of the remote plasma unit or the direct plasma unit generates a remote plasma and the other of the remote plasma unit or the direct plasma unit generates a direct plasma. The combination of a remote plasma unit and a direct plasma unit is used to remove, etch, clean, or treat residue on a substrate from previous processing and/or from native oxide formation. The combination of a remote plasma unit and direct plasma unit is used to deposit thin films on a substrate.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. A temperature of a pedestal comprising a cooling feature on which a substrate is located is set to less than or equal to 100° C. The substrate is exposed to a plasma treatment to remove chemical residual and/or impurities from features of the substrate including a metal bottom, dielectric sidewalls, and/or a field of dielectric and/or repair surface defects in the dielectric sidewalls and/or the field of the dielectric. The plasma treatment may be an oxygen plasma, for example, a direct oxygen plasma. Processing tools and computer readable media for practicing the method are also described.

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method includes supplying a vaporized precursor into a processing volume, supplying activated elements including ions and radicals from a remote plasma source, energizing the activated elements using RF source power at a first duty cycle to react with the vaporized precursor to deposit an SiNHx film onto a substrate disposed in the processing volume, supplying a first process gas from the remote plasma source while providing RF bias power at a second duty cycle different from the first duty cycle to the substrate support to convert the SiNHx film to an SiOx film, supplying a process gas mixture formed from a second process gas supplied from the remote plasma source and a third process gas supplied from the gas supply while providing RF bias power at the second duty cycle to the substrate support, and annealing the substrate.

Abstract: The present disclosure is generally related to 3D imaging capable OLED displays. A light field display comprises an array of 3D light field pixels, each of which comprises an array of corrugated OLED pixels, a metasurface layer disposed adjacent to the array of 3D light field pixels, and a plurality of median layers disposed between the metasurface layer and the corrugated OLED pixels. Each of the corrugated OLED pixels comprises primary or non-primary color subpixels, and produces a different view of an image through the median layers to the metasurface to form a 3D image. The corrugated OLED pixels combined with a cavity effect reduce a divergence of emitted light to enable effective beam direction manipulation by the metasurface. The metasurface having a higher refractive index and a smaller filling factor enables the deflection and direction of the emitted light from the corrugated OLED pixels to be well controlled.

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a physical vapor deposition processing chamber comprises a chamber body defining a processing volume, a substrate support disposed within the processing volume and comprising a substrate support surface configured to support a substrate, a power supply configured to energize a target for sputtering material toward the substrate, an electromagnet operably coupled to the chamber body and positioned to form electromagnetic filed lines through a sheath above the substrate during sputtering for directing sputtered material toward the substrate, and a controller operably coupled to the physical vapor deposition processing chamber for controlling the electromagnet based on a recipe comprising a pulsing schedule for pulsing the electromagnet during operation to control directionality of ions relative to a feature on the substrate.