Abstract: A multiplexing data communication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a T1 line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of the fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).

Abstract: A multiplexing data communication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a T1 line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of a fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).

Abstract: In a communications system (10), data is transferred from a physical interface section (64) and two processors, a receive processor (66) and a transmit processor (68). The data is transferred from the physical interface (64) to the receive processor (66) through a receive fifo (112). Data is transferred from the transmit processor (68) to the physical interface (64) through a transmit fifo (110). To prevent the transmit processor (68) and the receive processor (66) from processing data faster than the physical interface (64), clock disabling circuits (1030 and 1032) are utilized wherein the system clock (1033) to the receive processor (66) will be disabled when both the receive fifo (112) is empty and the current instruction performs a read from the receive fifo (112). The system clock (1050) to the transmit processor (68) will be disabled when both the transmit fifo (110) is full and the current instruction executes a write to the transmit fifo.

Abstract: A multiplexing data commmunication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a Tl line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of a fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).