Patents Assigned to Aristos Logic Corporation
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Patent number: 7421520Abstract: An I/O controller having separate command and data paths, thereby eliminating the bandwidth used by the commands and thus increasing bandwidth available to the data buses. Additionally, the I/O controller uses multiple dedicated data paths, for example, dedicated distributed buses, and provides increased speed due to improved hardware integration. The I/O controller employs distributed processing methods that decouple the external microprocessor from much of the decision-making, thereby providing improved operating efficiency and thus more useable bandwidth at any given clock frequency. Accordingly, the I/O controller is capable of maximizing I/O operations (IOPS) on all I/O ports by functioning at the rate of I/O connections to hosts and storage elements without becoming a bottleneck.Type: GrantFiled: August 27, 2004Date of Patent: September 2, 2008Assignee: Aristos Logic CorporationInventors: Virgil V. Wilkins, Robert L. Horn
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Patent number: 7412563Abstract: A method of calculating single and dual parity for a networked array of storage elements is presented. The method includes deriving a first set of n relationships where each of the first set of n relationships consists of an XOR statement equaling zero. Each of the first set of n relationships contains n data symbols from n storage elements and one parity symbol from a first set of parity symbols. The method also includes deriving a second set of n+1 relationships where each of the second set of n+1 relationships consists of an XOR statement equaling zero, containing at least n?1 data symbols from at least n?1 storage elements and one parity symbol from a second set of parity symbols. Using both the first and second sets of derived relationships, scripts are generated to resolve unresolved symbols resulting from possible single- and dual-storage element failure combinations.Type: GrantFiled: August 4, 2005Date of Patent: August 12, 2008Assignee: Aristos Logic CorporationInventors: Sanjay Subbarao, Kenneth W. Brinkerhoff
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Patent number: 7404021Abstract: An integrated I/O controller in an integrated circuit is provided for centralized data management. The integrated circuit includes a host interface, a disk interface, and a mapping controller implemented in hardware to speed data processing and provide fault tolerance as exemplified with RAID configurations. The mapping controller provides block mapping across a plurality of peripherals or disk drives in a disk array. The integrated I/O controller can be utilized in storage area network systems and network area storage systems as well as other networking systems or devices.Type: GrantFiled: August 6, 2004Date of Patent: July 22, 2008Assignee: Aristos Logic CorporationInventors: Virgil Wilkins, Robert Horn, Marc Acosta, Sanjay Mathur
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Patent number: 7353334Abstract: A system for and method of increasing performance and manageability of storage area networks using optimized cache setting and handling policies. Initial cache management policies are set on a volume or zone basis, performance statistics are gathered based on preset statistical criteria, and policies are then set according to the goal of reaching particular system performance goals. Cache performance is optimized by customizing individual cache policies according to the underlying processing needs of each volume or sub-volume within the networked storage system. Cache parameter settings are optimized in a different way depending on whether the bulk of commands processed in the volume or sub-volume are pseudo-sequential or random, as well as other system-specific considerations.Type: GrantFiled: August 11, 2003Date of Patent: April 1, 2008Assignee: Aristos Logic CorporationInventors: Robert L. Horn, Marc E. Acosta
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Patent number: 7287121Abstract: A method of predictive baseline volume profile creation for new volumes in a networked storage system and a system for dynamically reevaluating system performance and needs to create an optimized and efficient use of system resources by changing volume profiles as necessary. The system gathers statistical data and analyzes the information through algorithms to arrive at an optimal configuration for volume clusters. Clusters are then reallocated and reassigned to match the ideal system configuration for that point in time. The system continually reevaluates and readjusts its performance to meet throughput requirements specified in the quality of service agreement.Type: GrantFiled: December 23, 2003Date of Patent: October 23, 2007Assignee: Aristos Logic CorporationInventors: Robert L. Horn, Virgil V. Wilkins
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Patent number: 7162579Abstract: A network storage system includes a network storage system controller/virtualizer which includes at least one transaction processor. When a host access request is received by the network storage system controller/virtualizer, the transaction processor calculates one or more cost functions. In one exemplary embodiment, a cost function associated with storage system volume load and a cost function associated with communication path load are calculated. The cost function result(s) are utilized by the storage system controller/virtualizer to form a request for servicing the host access request while balancing the load of the network storage system.Type: GrantFiled: August 11, 2003Date of Patent: January 9, 2007Assignee: Aristos Logic CorporationInventors: Robert L. Horn, Virgil V. Wilkins
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Patent number: 7162582Abstract: A virtualizer module/element and a networked storage controller architecture with a virtualization layer that includes virtualizer modules. The virtualizer modules contain storage controller functionality as well as a cache subsystem. The virtualizer module processes primary data commands received from a host processor to determine if the cache subsystem of the virtualizer can service the data request or if it should be sent to a command mapper to retrieve the data from a downstream storage element. The cache subsystem of the virtualizer module thus enables reduced latency in the networked storage system as well as better management of storage devices and resources. The virtualizer module also facilitates predictive reads and read-ahead operations as well as coalesced write requests to a given storage device in order to increase system performance and storage device longevity.Type: GrantFiled: November 17, 2003Date of Patent: January 9, 2007Assignee: Aristos Logic CorporationInventors: Robert L. Horn, Virgil V. Wilkins
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Patent number: 7139931Abstract: A method of volume rebuilding in a RAID for a networked storage system in which portions of a hard disk drive under rebuild are progressively made available to the system during the rebuild process as the portions are rebuilt. The impact of rebuild activity on system performance is controllable by allowing non-rebuild requests to throttle rebuild requests.Type: GrantFiled: November 18, 2002Date of Patent: November 21, 2006Assignee: Aristos Logic CorporationInventor: Robert Horn
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Patent number: 7089381Abstract: A storage element pending command queue prioritization system using multiple pending queues each assigned to a particular RAID command type. Pending commands from each of the queues are organized in such a way that lower priority commands are guaranteed a fixed amount of storage element bandwidth. Storage element throughput is optimized by limiting higher priority commands to a maximum service level and processing lower priority requests with the added storage element bandwidth, allowing lower priority requests to exceed their minimum service levels.Type: GrantFiled: December 23, 2003Date of Patent: August 8, 2006Assignee: Aristos Logic CorporationInventors: Robert L. Horn, Virgil V. Wilkins
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Patent number: 7069382Abstract: A method of efficiently preventing data loss, specifically a RAID 5 write hole, in data storage system by storing valid parity information at the storage controller level during data write operations. The method employs the use of redundant data structures that hold metadata specific to outstanding writes and parity information. The method uses the redundant data structures to recreate the write commands and data when a system failure occurs before the writes have completed.Type: GrantFiled: December 23, 2003Date of Patent: June 27, 2006Assignee: Aristos Logic CorporationInventors: Robert L. Horn, Virgil V. Wilkins
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Patent number: 7043610Abstract: A disk array includes a system and method for cache management and conflict detection. Incoming host commands are processed by a storage controller, which identifies a set of at least one cache segment descriptor (CSD) associated with the requested address range. Command conflict detection can be quickly performed by examining the state information of each CSD associated with the command. The use of CSDs therefore permits the present invention to rapidly and efficiently perform read and write commands and detect conflicts.Type: GrantFiled: May 5, 2003Date of Patent: May 9, 2006Assignee: Aristos Logic CorporationInventors: Robert Horn, Biswajit Khandai
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Patent number: 7028297Abstract: A transaction processor pipeline architecture and associated apparatus for processing multiple queued transaction requests incorporates multiple processing elements working in parallel. Each processing element is configured to perform a specific function within the transaction processor system. Certain processing elements are assigned as function controllers, which are assigned to process specific transaction request subtask categories and may be augmented with dedicated hardware to accelerate certain subtask functions. Other processing elements are configured as list managers, which are optimized for managing data structure operations in memory. The processing elements are connected by a cross-point interconnect. The transaction processor system is configurable and scalable based on application needs.Type: GrantFiled: May 5, 2003Date of Patent: April 11, 2006Assignee: Aristos Logic CorporationInventors: Robert L. Horn, Virgil V. Wilkins, Mark D. Myran, David S. Walls, Gnanashanmugam Elumalai
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Patent number: 6912643Abstract: The present invention provides an architecture and method for increasing the performance and resource utilization of networked storage architectures by use of hardware-based storage element mapping. The architecture utilizes a customized programmable processing element to map host read or write commands to physical storage element commands. The present invention uses a plurality of data structures, such as tables, to map host read and write commands to physical storage elements. The hardware-based storage element mapping controller uses the tables, including a mapping segment descriptor table, to map from global address space addresses to physical storage element addresses.Type: GrantFiled: November 15, 2002Date of Patent: June 28, 2005Assignee: Aristos Logic CorporationInventor: Robert Horn