Abstract: A digital circuit including a Booth encoder having inputs for receiving a plurality of adjacent bits of a first binary input number, and an encoder control input for allowing selection between multiplication of first and second binary input numbers and multiplication of the pairs of binary numbers smaller than the first or second input number, the encoder being configured to encode the bits of the first binary input number dependent on the encoder control input to generate Booth encoded outputs for use in selection of a partial product, the Booth encoder being for use with a selector having inputs for receiving a plurality of adjacent bits of the second binary input number, and for receiving the Booth encoded outputs from the encoder, the selector being configured to select a partial product bit according to the Booth encoded outputs and the bits of the second binary input number.

Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

Abstract: A maximum likelihood detector receiving a data stream corresponding to ideal values which may include noise, and outputting information specifying a sequence of states of maximum likelihood selected from possible states corresponding to the data stream according to weighting value selections made by the processors, the ideal values being determined by the possible states, including: a pre-processor to obtain first weighting values; processors in a hierarchy, each processor in a select level of the hierarchy is programmed to use, respectively, a plurality of the weighting values to calculate subsequent weighting values indicating respective likelihoods that a section of the data stream values corresponds to each of a plurality of possible state sequences, for each possible initial state and each possible final state, to select further weighting value of highest likelihood corresponding to a state sequence from the initial state to the final state.

Abstract: Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively logically AND and OR combining respective bits of binary inputs; logic generating high output if a carry is generated out of a first group of most significant bits of binary input or if carry propagate function bits for the most significant bits are all high; logic for receiving bit level carry generate and propagate function bits for binary inputs to generate high output if any of carry generate function bits for the most significant bits are high or if carry is generated out of another group of least significant bits of binary input; and logic for generating the carry or sum bit output by combining outputs of the two logics.

Abstract: Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals; second logic receiving the first and second signals generated by first logic and generating an output signal as XOR of first signal and third input signal. Second logic includes at least two pass gates. First gate terminal of the first pass gate receives third input signal. A second gate terminal of the first pass gate receives the inverse of third input signal. First gate terminal of the second pass gate receives the inverse of the third input signal. Second gate terminal of the second pass gate receives the third input signal. Input terminals of the first and second pass gates receive the first signal and the second signal respectively. Pass gate output terminals generate the output signal.

Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.

Abstract: A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic having two logic parts that each include NOR and NAND gates, and having two first-level inputs for receiving the binary inputs and two first-level outputs; and second logic having four second-level outputs, four second-level inputs for receiving second-level binary inputs and connected to the four first-level outputs, NAND gate, first gate generating logical OR combinations and NAND combining the logical OR combination with two other second-level binary inputs, a second gate generating logical OR combinations of two pairs of second-level binary inputs and NAND combining the logical OR combinations, and a NOR gate; wherein one of four binary outputs is generated at each of the four outputs.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary number with each other bit of another binary number is generated having a reduced from in order to reduce the steps required in array reduction.

Abstract: Circuit for selecting a second set of binary inputs according to the number of high input signals applied to a first input set. A first subcircuit has the first input set, logic generating control output signals, each control output signal represents whether the first input set has exactly a predetermined number of high input signals. Each control output signal corresponds to a different predetermined number of high input signals. A second subcircuit has a second input set, a set of control inputs for receiving control output signals from the first subcircuit, and logic including a plurality of switches including one or more pass gates. Each switching component switches to connect or isolate one of the second input set to a common output. The control inputs control the switches. The first and second subcircuits are configured such that only one switch can be switched to connect at a time.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.