Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of color values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colors of the individual texture elements using that generated set of colors. As well as the individual texture data blocks, a header data block encoding a base set of colors is generated. This base color set defines a set of colors that is used to generate the colors to be used when reproducing each individual encoded texture data block.

Abstract: When an alpha test is performed as part of the rendering process in a multisampled graphics processing pipeline, rather than taking the single alpha value initially defined for each fragment an individual alpha value is generated in respect of each of covered sampling position that the fragment in question is being used to render. The individual alpha values estimated for each sample position are then individually compared with a threshold alpha value defined for the alpha test, and the result of this alpha test comparison is used to decide either keep or discard the sample position from further processing.

Abstract: A graphics processing platform includes a rasteriser 50 that receives primitives representing an image to be displayed for processing. The rasteriser 50 determines which sets of sampling points of the image include sampling points that are covered by a given primitive, and then generates a fragment for rendering for each set of sampling points found to include a sampling point that is covered by the primitive and passes those fragments to a renderer 51 for rendering. The renderer 51 carries out rendering operations on the fragments that it receives, and stores the rendered fragment data in tile buffers 52. The rendered fragment data is stored in multiple copies in the appropriate sample positions in the tile buffers 52, so as to provide a separate set of fragment data for each individual sample position taken of the image. The data from the tile buffers 52 is input to a downsampling unit 53, and thence output to a frame buffer 54 of a display device 55 for display.

Abstract: A graphics processing platform includes a rasteriser 50 that receives primitives representing an image to be displayed for processing. The rasteriser 50 determines which sets of sampling points of the image include sampling points that are covered by a given primitive, and then generates a fragment for rendering for each set of sampling points found to include a sampling point that is covered by the primitive and passes those fragments to a renderer 51 for rendering. The renderer 51 carries out rendering operations on the fragments that it receives, and stores the rendered fragment data in tile buffers 52. The rendered fragment data is stored in multiple copies in the appropriate sample positions in the tile buffers 52, so as to provide a separate set of fragment data for each individual sample position taken of the image. The data from the tile buffers 52 is input to a downsampling unit 53, and thence output to a frame buffer 54 of a display device 55 for display.

Abstract: A microprocessor pipeline arrangement 1 includes a plurality of functional units P1, P2, P3, . . . , PN. A number of the functional units P1, P3, PN have access to a respective cache memory C1, C3, CN from which it can retrieve data needed to process threads that pass through the pipeline. The pipeline arrangement 1 also includes a number of monitors to determine when the system enters a state of livelock (e.g. inter-cache livelocks, intra-cache livelocks and/or “near-livelock” situations): a top-level monitor MT to detect livelock situations in the pipeline as a whole; and second-level (“local”) monitors M1 and M3 associated with individual caches C1 and C3. If the system is determined to have entered a livelock state, e.g. by the top-level monitor MT, the number of threads able to change the contents of one or more of the caches C1, C3, CN is reduced.

Abstract: A microprocessor pipeline arrangement 1 includes a plurality of functional units 2, 3, 4, 5 and 6. Each functional unit 2, 3, 4, 5, 6 also has access to a respective cache memory 7, 8, 9, 10, 11. Threads for processing are received by the first functional unit 2 from an external source 12, and output by an end functional unit 6 of the pipeline to an output target 13. If a thread encounters a cache-miss on its passage through the pipeline, the thread is allowed to continue to pass through the pipeline in the normal manner. However, when the thread reaches the end of the pipeline, it is sent via a loopback path 14 back to the beginning of the pipeline to be sent through the pipeline again. In this way, any thread that has not completed its processing on passing through the pipeline can be sent through the pipeline again to allow the processing of the thread to be completed.

Abstract: A memory management arrangement includes a memory management unit 1, a cache memory 2 and a queue arrangement 3. The queue 3 is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit 1 via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit 1 experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache 2, the memory management unit 1 operates to place the failed memory access request in the replay queue 3, and allows subsequent memory access requests to continue. The failed memory access requests in the queue 3 are then continuously circulated through the memory management unit 1 from the queue alternately with new memory access requests from other access initiators 4.

Abstract: When an alpha test is performed as part of the rendering process in a multisampled graphics processing pipeline, rather than taking the single alpha value initially defined for each fragment 80, 81, 82, 83, an individual alpha value is generated in respect of each of covered sampling position that the fragment in question is being used to render. The individual alpha values estimated for each sample position are then individually compared with a threshold alpha value defined for the alpha test, and the result of this alpha test comparison is used to decide either keep or discard the sample position from further processing.

Abstract: In a graphics processing system, the left, right, top and bottom edge planes for the purposes of clipping are set to the maximum values that can be represented using floating-point format numbers, vertex positions are snapped to a grid of predefined vertex positions, and the precision of selected vertices is prioritised when deriving edge functions for a given primitive. In respect of the depth near and far clipping planes, those planes are set to the maximum floating-point number format that can be represented for Z in the graphics system, but then fragments that have a Z value that falls outside the range zero to one are discarded by means of a depth test. In respect of the eye-plane, the need for clipping is avoided by instead modifying the edge equations generated for a primitive in dependence on the sign of the W value for each vertex of the primitive.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of colour values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colours of the individual texture elements using that generated set of colours. As well as the individual texture data blocks, a header data block encoding a base set of colours is generated. This base colour set defines a set of colours that is used to generate the colours to be used when reproducing each individual encoded texture data block.

Abstract: A graphics processor 20 includes a graphics object list building unit 28 that determines the location of each draw call in a scene to be rendered and generates a list of draw calls for each sub-region (tile) that the scene to be rendered is divided into. The draw call lists are stored in a memory 23. A graphics object selection unit 29 of a renderer 22 of the graphics processor 20 then determines which draw call is to be rendered next by considering the draw call list 26 stored in the memory 23 for the sub-region (tile) of the scene that is currently being rendered.

Abstract: A scene 50 to be rendered is divided into plural individual sub-regions or tiles 51. The individual sub-regions 51 are also grouped into differing groups of sets of plural sub-regions. There is a top level layer comprising a set 54 of 8×8 sub-regions which encompasses the entire scene area 50. There is then a group of four 4×4 sets of sub-regions 53, then a group of sixteen 2×2 sets of sub-regions 52, and finally a layer comprising the 64 single sub-regions 51. A primitive list building unit takes each primitive 80 in turn, determines a location for that primitive, compares the primitive's location with the locations of the sub-regions 51 and the locations of the sets of sub-regions 52, 53 and 54, and allocates the primitive to respective primitive lists for the sub-regions and sets of sub-regions accordingly.