Abstract: A fault-tolerant failsafe computer voting system including a first voting module that generates a first key based on a comparison between a first data packet and a copy of a second data packet. The first voting module determines whether the first key and a second key are valid keys. The second data packet is a copy of the first data packet. A second voting module generates the second key based on a comparison between the second data packet and a copy of the first data packet. A processing module generates an outgoing data packet based on the first data packet in response to determining whether the first key and the second key are valid keys. The first voting module is inhibited from generating the second key and the second voting module is inhibited from generating the first key.

Abstract: A system includes a first fail-safe chassis (FSC) receives module health signals from a plurality of modules and generates a first chassis health signal. The chassis health signal includes first and second portions. A plurality of modules receives the chassis health signal. The FSC determines whether one or more of the module heals signals indicates an associated module is unhealthy by comparing the module health signals and a predetermined health value. The FSC selectively de-asserts the first chassis health signal based on the comparison. A second FSC operates similarly. A safety relay box determines the health of the system in accordance with the first and second chassis health signals.

Abstract: A canister system having a cylindrical housing and a modular electronic rack system disposed within the cylindrical housing. The modular electronic rack system includes a thermal contact member that is in at least selective physical contact with an interior surface of the cylindrical housing to permit conductive heat transfer there through. An input/output device extends along at least a portion of the modular electronic rack system and includes a power input and a signal output electrically coupled thereto. A plurality of electronic slots disposed at a position generally along the modular electronic rack system is provided.

Abstract: An apparatus is disclosed for restricting air flow through an electronics enclosure. The apparatus may include a panel having at least one edge adapted to be secured to a surface of the electronics enclosure to thus place the panel in a path of a cooling air flow flowing through a cardcage portion of the enclosure. The panel may have a footprint that at least substantially fills an opening through which said cooling air flow flows through said cardcage portion of the enclosure. The panel may have a plurality of openings so that the panel reduces a volume of a cooling air flow flowing through the panel by a predetermined desired degree, and thus reduces a volume of the air flow through the cardcage to a desired volume.

Abstract: A module health system includes a module health circuit comprising a hardware register that is set to a first value in response to the system starting, an application register that is set to the first value in response to the system starting and a watchdog timer register that is set to the first value in response to the system starting. The system further includes a power on self-test that determines whether the system has passed a plurality of tests and that selectively sets the hardware register to a second value based on the determination, an external software application that determines whether a safety critical system is healthy and selectively sets the application register based on the determination, a watchdog timer application that selectively sets the watchdog timer register, a central processing unit that determines whether to de-assert a module health signal.

Abstract: A system includes a first node that generates a first clock signal having a frequency, generates a plurality of data packets, modifies the data packets to include data indicative of time and phase information associated with the first node, and transmits the data packets. A second node receives the plurality of data packets and the first clock signal, determines the time and phase information based on the plurality of data packets, determines the frequency based on the first clock signal, and generates at least one of a second clock signal and a local time based on the time and phase information and the frequency of the first clock signal.

Abstract: A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.

Abstract: A cooling system having integrated cold plate extending member and cold plate for an electronics enclosure includes a chassis having multiple heat producing boards positioned in side-by-side parallel configuration having successive ones of the boards separated by a cavity thereby defining multiple ones of the cavities. A cold plate assembly includes a base unit of a thermally conductive material. The cold plate assembly also includes multiple cold plate extending members connected to the base unit. Successive ones of the cold plate extending members are spaced to be slidably received in one of the cavities such that the cold plate extending member received between any two successive boards is in direct contact with both of the successive ones of the boards.

Abstract: A digital signal interface includes a multiplexer coupled to receive a plurality of data signals from at least one of a microprocessor, a microcontroller, or a field-programmable gate array (FPGA), the multiplexer multiplexing the plurality of data signals. The interface further includes a serializer/deserializer (SerDes) transceiver coupled to receive the multiplexed data signals, the SerDes transceiver serializing the multiplexed data signals and transmitting the serialized data signals.

Abstract: A dual redundant computer safety relay box system includes first and second fail-safe computing systems (FSCs) individually mounted to first and second printed circuit boards. Each FSC includes two computing modules (CPUs) designated as a first CPU and a second CPU. The first and second FSC's are both connected to a safety relay box. The printed circuit boards are isolable from each other permitting maintenance on one of the printed circuit boards while operation of the FSC of the other printed circuit board is maintained. In each FSC a health signal generated from the first and second printed circuit boards of the first and second CPUs defines a multi-level dynamic pulse signal. Presence of the dynamic pulse signal produces an output identified as each of a first and a second healthy indication signal from each of the CPUs of one of the first or second FSCs.

Abstract: A module health system includes a module health circuit comprising a hardware register that is set to a first value in response to the system starting, an application register that is set to the first value in response to the system starting and a watchdog timer register that is set to the first value in response to the system starting. The system further includes a power on self-test that determines whether the system has passed a plurality of tests and that selectively sets the hardware register to a second value based on the determination, an external software application that determines whether a safety critical system is healthy and selectively sets the application register based on the determination, a watchdog timer application that selectively sets the watchdog timer register, a central processing unit that determines whether to de-assert a module health signal.

Abstract: A cooling system having integrated cold plate extending member and cold plate for an electronics enclosure includes a chassis having multiple heat producing boards positioned in side-by-side parallel configuration having successive ones of the boards separated by a cavity thereby defining multiple ones of the cavities. A cold plate assembly includes a base unit of a thermally conductive material. The cold plate assembly also includes multiple cold plate extending members connected to the base unit. Successive ones of the cold plate extending members are spaced to be slideably received in one of the cavities such that the cold plate extending member received between any two successive boards is in direct contact with both of the successive ones of the boards.

Abstract: A system includes a safety relevant component that generates a data packet in response to receiving a request to perform a task and that communicates the data packet. The system further includes a first fail-safe chassis (FSC) that continuously generates a first chassis health signal, that determines whether the data packet is valid, and that selectively determines whether to de-assert the first chassis health signal based on the determination. The system also includes a second FSC that continuously generates a second chassis health signal, that determines whether a copy of the data packet is valid, and that selectively determines whether to de-assert the second chassis health signal based on the determination. The system further includes a safety relay box module that determines whether to instruct the first FSC to operate in a predetermined mode based on the first chassis health signal and the second chassis health signal.

Abstract: A fault-tolerant failsafe computer voting system includes a switch module that generates a first copy of a first data packet and a second copy of the first data packet and that communicates the first copy and the second copy. The system also includes a first voting module that generates a first packet signature based on the first copy and communicates the first packet signature. The system further includes a second voting module that generates a second packet signature based on the second copy and communicates the second packet signature.

Abstract: A canister system having a cylindrical housing, having at least one enclosed end, and a modular electronic rack system disposed within the cylindrical housing. The modular electronic rack system including an input/output device extending along at least a portion of the modular electronic rack system. The modular electronic rack system further having a power input and a signal output electrically coupled to the input/output device—at least one of the power input and the signal output extending through the at least one enclosed end of the cylindrical housing at a first sealed terminal. The canister system further having a first alignment system for physically aligning an electronic connection with the sealed terminal. The electronic connection having physically engaging features extending from the cylindrical housing to align the electronic connection therewith.

Abstract: A circuit board assembly for installation in a cabinet includes a first standards based size first mounting frame portion having a PCB mounted thereto. A second mounting frame portion is connected to the first mounting frame portion having no portion of the PCB connected thereto. A combination size of the first and second mounting frames defines a larger second standards based size. Multiple heat transfer components may be connected to the first or second mounting frame portion provide a conduction/convection cooling path. The first mounting frame portion may include a first false board edge and the second mounting frame portion includes one or more false board edge(s) positioned laterally and oppositely directed to the first false board edge. The first and second false board edges are slidably received in opposed slots created in a cabinet.

Abstract: A system includes a safety relevant component that generates a data packet in response to receiving a request to perform a task and that communicates the data packet. The system further includes a first fail-safe chassis (FSC) that continuously generates a first and second chassis health signals, that determines whether the data packet is valid, and that selectively determines whether to de-assert the first and second chassis health signals based on the determination. The system also includes a second FSC that continuously generates a third a fourth chassis health signals, that determines whether a data packet is valid, and that selectively determines whether to de-assert the third and fourth chassis health signals based on the determination. The system includes a direct connect algorithm state machine that determines whether to instruct the one of the first and second FSCs to operate in a predetermined mode based on the chassis health signals.

Abstract: A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.

Abstract: A fault-tolerant failsafe computer system including an inter-processor communication channel includes a transmission control module that encodes a first data packet and communicates a first encoded copy of the first data packet and a second encoded copy of the first data packet. The system also includes a receiver control module that i) receives a first encoded copy of a second data packet and a second encoded copy of the second data packet and ii) decodes the first encoded copy and the second encoded copy. The system further includes a de-duplication module that receives a plurality of data packets and communicates at least one unique data packet of the plurality of data packets.

Abstract: A system includes a first application that writes a first plurality of tasks to a first memory buffer; a second memory buffer that receives a copy of the first plurality of tasks; a second application that writes a second plurality of tasks to a third memory buffer; and a fourth memory buffer that receives a copy of the second plurality of tasks. The system further includes a first comparison module that generates a first voting signal based on a first comparison between a first task and a second task. The system further includes a second comparison module that generates a second voting signal based on a second comparison between the first task and the second task. The system further includes a first central processing unit (CPU) that selectively determines whether to de-assert a module health signal based on the first voting signal and the second voting signal.