Abstract: A power supply for providing a modulated output voltage to a load is disclosed. According to various embodiments, the power supply comprises a plurality of parallel-connected switch-mode power modules and a controller. The controller is connected to each of the power modules and is for controlling the duty cycles of the respective power modules such that the power modules have a common duty cycle in steady state, but in a phase-shifted or “interleaved” manner. In addition, the controller is for controlling the output voltage of the power converter by controlling the ratio of power modules in the forward state at a time to the total number of power modules. In this way, by providing a sufficiently large number of power modules, arbitrarily low output voltage amplitudes and intra-level oscillations can be achieved. Further, the rate of modulation of the output voltage can exceed the switching frequency (f=1/T, where T is the switching period) of the power modules.

Abstract: An ORing element for use in a power supply and/or power system. The ORing element may include a field effect transistor (FET), a first bi-polar transistor and a second bi-polar transistor. The FET may be electrically connected between an input and an output. The first bipolar transistor may have an emitter electrically connected to the source of the FET and a collector electrically connected to a gate of the FET. The second bi-polar transistor may be diode connected, with its emitter electrically connected to its base. The emitter of the second bi-polar transistor may also be electrically connected to the base of the first bi-polar transistor. The collector of the second bi-polar transistor may be electrically connected to the drain of the FET.

Abstract: A power supply for providing a modulated output voltage to a load is disclosed. According to various embodiments, the power supply comprises a plurality of parallel-connected switch-mode power modules and a controller. The controller is connected to each of the power modules and is for controlling the duty cycles of the respective power modules such that the power modules have a common duty cycle in steady state, but in a phase-shifted or “interleaved” manner. In addition, the controller is for controlling the output voltage of the power converter by controlling the ratio of power modules in the forward state at a time to the total number of power modules. In this way, by providing a sufficiently large number of power modules, arbitrarily low output voltage amplitudes and intra-level oscillations can be achieved. Further, the rate of modulation of the output voltage can exceed the switching frequency (f=1/T, where T is the switching period) of the power modules.

Abstract: A method of determining a source of data received over a two-wire master-slave communication bus includes monitoring with a slave assembly a plurality of clock signals each generated by a master device and determining the source of data received over the two-wire master-slave communication bus based on the monitored clock signals. Examples of suitable slave assemblies and systems for performing the method are also disclosed.

Abstract: A power supply for providing a modulated output voltage to a load is disclosed. According to various embodiments, the power supply comprises a plurality of parallel-connected switch-mode power modules and a controller. The controller is connected to each of the power modules and is for controlling the duty cycles of the respective power modules such that the power modules have a common duty cycle in steady state, but in a phase-shifted or “interleaved” manner. In addition, the controller is for controlling the output voltage of the power converter by controlling the ratio of power modules in the forward state at a time to the total number of power modules. In this way, by providing a sufficiently large number of power modules, arbitrarily low output voltage amplitudes and intra-level oscillations can be achieved. Further, the rate of modulation of the output voltage can exceed the switching frequency (f=1/T, where T is the switching period) of the power modules.

Abstract: A transformer. The transformer includes a first conductor plate, a second conductor plate, a plate positioning member, an insulated wire, and a magnetic core. The second conductor plate is spaced apart from and electrically connected to the first conductor plate. The plate positioning member is in contact with and surrounded by the first and second conductor plates. The insulated wire is wound around the plate positioning member and between the first and second conductor plates. The magnetic core includes a portion surrounded by the plate positioning member, the first conductor plate, the second conductor plate, and the insulated wire.

Abstract: A power converter is disclosed. According to one embodiment, the power converter includes a first stage comprising a current source and a second stage comprising n output circuits for converting the current signal into n corresponding output voltages. Each of the n output circuits includes an output switch responsive to a corresponding nth control signal for regulating the corresponding nth output voltage. The second stage further comprises a controller for generating the n control signals. The controller includes, for each of the n output circuits, an error amplifier, a waveform generator, and a summing circuit. Each error amplifier is configured to generate an output signal based upon a comparison of the output voltage of the nth output circuit and a corresponding nth reference voltage. Each waveform generator generates a waveform signal.

Abstract: A power converter is disclosed. According to one embodiment, the power converter includes a first stage including a current source for generating a current signal, and a second stage. The second stage includes n output circuits coupled to the current source for converting the current signal into n corresponding output voltages. Each of the n output circuits includes an output switch responsive to a corresponding nth control signal for regulating the corresponding nth output voltage. The second stage further includes a controller for generating the n control signals. The controller includes, for each of the n output circuits, an error amplifier, a waveform generator, and a summing circuit. Each error amplifier generates an output signal based upon a comparison of the output voltage of the nth output circuit and a corresponding nth reference voltage. Each waveform generator generates a waveform signal.

Abstract: The present invention is directed to a digital controller for adjusting the duty ratio a pulse width modulation control signal used to control a power switch of a switch mode power converter. According to various embodiments, the digital controller comprises a voltage compensator module for generating a first signal (Dvoltage) representative of the duty ratio of the control signal based on a difference between an output voltage of the converter and a reference voltage. The controller also includes a current compensator module for generating a second signal (Dcorrection) representative of a modification to the duty ratio of the control signal based on an output current of the converter. A subtraction module subtracts the second signal (Dcorrection) from the first signal (Dvoltage) to thereby generate a third signal (D), which is used by a duty ratio PWM generator module to generate the pulse width modulation control signal with the appropriate duty ratio.

Abstract: A DC-DC converter includes a control circuit for generating a pulse width modulated signal based on a voltage of an output node. A first switch is connected to conduct during pulses, and a second switch conducts between pulses. The first switch is connected to an internal power node and the second is connected to a current return node. There is a common node between the first switch and the second switch. The voltage of the common node is supplied to an output node. An input power switch supplies voltage to the internal power node. An over-voltage protection circuit is connected to receive an over-voltage fault signal from the control circuit, and it is connected to control a bias of the control terminal of the input power switch to cause the input power switch not to conduct during an event causing an over-voltage fault signal, whereby a load connected to the output node is protected.

Abstract: A power converter that includes a transformer, a bridge input circuit, a self-driven synchronous rectifier circuit, a gate drive circuit, and a gate drive shutdown circuit. The transformer includes a primary winding connected to the bridge input circuit, a first secondary winding, and a second secondary winding. The self-driven synchronous rectifier circuit is connected to the first secondary winding and includes a first synchronous rectifier for rectifying a voltage across the first secondary winding. The first synchronous rectifier includes a control terminal responsive to a voltage across the second secondary winding. The gate drive circuit includes a first diode connected to the control terminal of the first synchronous rectifier for introducing a dc level shift thereto.

Abstract: A PFC AC-to-DC power supply is disclosed. According to various embodiments, the PFC AC-to-DC power supply comprises a switching converter comprising at least one main power switch and a PFC controller for controlling the at least one main power switch. The PFC controller may comprise a processing unit comprising a processor and a memory having firmware stored thereon which, when executed by the processor, causes the processor to compute an input current set point for the AC-to-DC power supply based on the output voltage of the AC-to-DC power supply. The PFC controller may also comprise hardware circuitry in communication with the processing unit. The hardware circuitry may comprise a first a/d converter, such as a window a/d converter, for outputting a digital input current error value based on the input current of the AC-to-DC power supply and an analog form of the input current set point from the processing unit.

Abstract: An ORing element for use in a power supply and/or power system. The ORing element may include a field effect transistor (FET), a first bi-polar transistor and a second bi-polar transistor. The FET may be electrically connected between an input and an output. The first bipolar transistor may have an emitter electrically connected to the source of the FET and a collector electrically connected to a gate of the FET. The second bi-polar transistor may be diode connected, with its emitter electrically connected to its base. The emitter of the second bi-polar transistor may also be electrically connected to the base of the first bi-polar transistor. The collector of the second bi-polar transistor may be electrically connected to the drain of the FET.

Abstract: A method for determining a fan speed for a fan used to cool a payload is disclosed. The method includes, according to various embodiments, receiving a first signal indicative of a first fan speed and receiving a second signal indicative of a system temperature. The method further includes selecting a temperature setpoint based on the first fan speed and, based on a comparison of the system temperature and the selected temperature setpoint, computing a first fan speed output. A thermal management system and method for determining a speed-setpoint droop characteristic are also disclosed.

Abstract: A multi-layer printed circuit board. The multi-layer printed circuit board includes a first winding, and a first via connected to the first winding. The first winding includes a first edge. The first edge defines a first footprint. The first footprint surrounds and is proximate an opening defined by the printed circuit board. At least a portion of the first via is between the first footprint and the opening.

Abstract: The present invention is directed generally to a power supply. According to various embodiments, the power supply includes at least one DC/DC converter. The converter includes a primary switch controlled by a pulse width modulated control signal such that the primary switch is on for a D time period of each switching cycle of the converter and is off for a 1-D time period of each switching cycle. Also, the power supply includes a current sensing element connected in series with the primary switch. In addition, the power supply includes a current limit circuit connected to the current sensing element. The current limit circuit includes a functional circuit having a first input responsive to a first signal whose voltage is proportional to the output current of the converter during the D time period of the switching cycle of the converter.

Abstract: A programmable error amplifier (PEA) that may be used as part of a voltage regulation subsystem to control the output of a digitally programmable voltage source is disclosed. According to various embodiments, the PEA comprises an amplification circuit, an analog voltage sampling circuit and a digital reference voltage sampling circuit. The amplification circuit may employ a negative feedback configuration, and include an amplifier and a plurality of feedback capacitors. The analog voltage sampling circuit is responsive to an analog input voltage (such as the output of the programmable voltage source) and is coupled to the amplification circuit. During a first operational phase (the sampling phase), the analog voltage sampling circuit stores a charge dependent upon the analog input voltage, and during a second operational phase (the conversion phase), the analog voltage sampling circuit transfers the charge to the feedback capacitors of the amplification circuit.

Abstract: A heat spreader is disclosed. The heat spreader includes a body member, a first fin connected to the body member, a second fin connected to the body member, a third fin connected to the body member, and a fourth fin connected to the body member. The first and second fins define a first spacing therebetween. The second and third fins define a second spacing therebetween. The third and fourth fins define a third spacing therebetween. The second spacing is greater than the first spacing and the third spacing.

Abstract: A multi-lead surface mount interconnect. The interconnect includes a carrier, a first lead connected to the carrier, and a second lead connected to the carrier. The carrier defines a first receiving area and a second receiving area. The first lead includes a first planar surface for connection to a first printed circuit board and a second planar surface for connection to a second printed circuit board. The first planar surface is opposite the second planar surface. The second lead includes a third planar surface for connection to the first printed circuit board and a fourth planar surface for connection to the second printed circuit board. The third planar surface is opposite the fourth planar surface. The first planar surface is coplanar with the third planar surface. The second planar surface is coplanar with the fourth planar surface.

Abstract: A magnetic assembly for mounting to a circuit includes a winding and a core. The winding has a first end, a second end and a wound portion. Further, the core is disposed around at least a portion of the winding. The first end of the winding extends outward from the wound portion to define a linear support and the second end of the winding extends outward from the wound portion on an opposite side of the wound portion to define a point support. As such, the first and second ends of the winding are adapted to mount to the circuit.