Abstract: A differential amplifier circuit is provided. The differential amplifier circuit includes a differential amplifier, a first active inductor, a second active inductor, and a parameter circuit. The differential amplifier includes a first differential output terminal and a second differential output terminal. The first active inductor is coupled to the first differential output terminal. The second active inductor is coupled to the second differential output terminal. The parameter circuit is coupled between the first active inductor and the second active inductor. The parameter circuit provides at least one parameter. A low frequency gain, an equivalent impedance, and a bandwidth of the differential amplifier circuit are adjusted in response to the at least one parameter.

Abstract: A transmission circuit is provided. The transmission circuit includes a T-coil, a first resistance value generator, a second resistance value generator and a capacitance value generator. The first resistance value generator generates a first resistance value according to a first control signal. The second resistance value generator generates a second resistance value according to a second control signal. The capacitance value generator generates a capacitance value according to a third control signal. A gain spectrum of the transmission circuit is adjusted according to the first resistance value, the second resistance value and the capacitance value.

Abstract: A transmission circuit is provided. The transmission circuit includes a T-coil, a first resistance value generator, a second resistance value generator and a capacitance value generator. The first resistance value generator generates a first resistance value according to a first control signal. The second resistance value generator generates a second resistance value according to a second control signal. The capacitance value generator generates a capacitance value according to a third control signal. A gain spectrum of the transmission circuit is adjusted according to the first resistance value, the second resistance value and the capacitance value.

Abstract: A data storage apparatus and a data prediction method thereof are provided. The data storage apparatus includes a memory unit and a prediction unit. The prediction unit acquires a plurality of access location data of a plurality of data access actions of a prior access history of the memory unit. The prediction unit analyzes the prior access history of the memory unit. The prediction unit performs a quantification process on the access location data to acquire a plurality of quantized data corresponding to the prior access history. The prediction unit predicts a data pre-accessing target of the memory unit according to the quantized data.

Abstract: A management method for a data storage device is provided and includes the following steps: obtaining a plurality of association rules according to a plurality of previous access commands; building a plurality of look-up tables according to the association rules; receiving a current access command and determining whether the current access command corresponds to at least one of the look-up tables to obtain physical addresses of the current access command from the corresponding look-up table; predicting a look-up table corresponding to a subsequent access command based on these association rules; and pre-establishing the predicted look-up tables. The invention also provides a data storage system and a data storage device, which can implement the management method described above.

Abstract: A data storage apparatus and a data prediction method thereof are provided. The data storage apparatus includes a memory unit and a prediction unit. The prediction unit acquires a plurality of access location data of a plurality of data access actions of a prior access history of the memory unit. The prediction unit analyzes the prior access history of the memory unit. The prediction unit performs a quantification process on the access location data to acquire a plurality of quantized data corresponding to the prior access history. The prediction unit predicts a data pre-accessing target of the memory unit according to the quantized data.

Abstract: An eye diagram observation device is provided. The eye diagram observation device includes an eye diagram determination circuit and a clock generator. The eye diagram determination circuit obtains an eye diagram corresponding to an input signal pair based on a delayed sampling clock. The clock generator includes a voltage to time converter (VTC). The VTC generates a delayed clock based on a voltage value of an input voltage. The clock generator generates the delayed sampling clock based on the delayed clock. The eye diagram observation device may reduce power consumption and a layout area via the VTC.

Abstract: A bridge module is provided. The bridge module comprise a first transmission unit electrically connected to a host to receive a power status signal from the host; a second transmission unit electrically connected to a data transceiver device to have data transmission with the data transceiver device at a download data transmission speed; and a processing device electrically connected to the first transmission unit and the second transmission unit, and configured to adjust the download data transmission speed and a processor clock of the processing device according to the power status signal. An operation method is also provided.

Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.

Abstract: A bridge module is provided. The bridge module comprises a first transmission unit electrically connected to a host to transfer data with the host at an uplink data transmission rate; a second transmission unit electrically connected to a data transmission device to transfer data with the data transmission device at a downlink data transmission rate; and a processing device configured to adjust the downlink data transmission rate according to the uplink data transmission rate. A data transmission method is also provided.

Abstract: A disk managing method includes: receiving a host Frame Information Structure (FIS) including multiple host logical Block Address Range Entries (LBA Range Entries) from a host; determining whether the LBA Range Entries satisfy a speed up processing condition; generating a first and a second addresses corresponding to a first and a second hard disks according to the host LBA Range Entries; and outputting a first and a second hard disk FIS to the first and the second hard disk for management. The number of first and second hard disk LBA Range Entries in the first and the second hard disk FIS are respectively half of the number of the host LBA Range Entries.

Abstract: A synchronous transmission device includes a first communication port, a first bus instance and a second bus instance. The first communication port is connected to the first endpoint and the second endpoint. The first bus instance executes a first data transmission with the first endpoint according to a first node of a first schedule list. The first node corresponds to the first endpoint, and the first bus instance corresponds to the first communication port. When the first data transmission is executed, the first bus instance is further configured to determine whether the second bus instance is idle. When the second bus instance is idle, the first bus instance controls the second bus instance to execute a second data transmission with the second endpoint according to a second node of the first schedule list. The second node of the first schedule list corresponds to the second endpoint.

Abstract: A bridge device includes a first physical layer circuit, a first buffer memory, a DMA controller, and a processor. The first physical layer circuit is configured to connect to an upstream device. The first buffer memory is configured to store a first data and transfer data to the upstream device via the first physical layer circuit. The DMA controller is coupled to the first buffer memory and configured to access the first data in the first buffer memory to read and/or write a storage device correspondingly. The processor is coupled to the first buffer memory and the DMA controller. When the bridge device receives a clear feature command from the upstream device, the processor is configured to reset the first buffer memory and the DMA controller to stop the data transferring between the upstream device and the bridge device.

Abstract: A port multiplier system is provided. The port multiplier system comprises a first port multiplier and a second port multiplier. The first port multiplier is configured to receive a plurality of first frame information structures from a host. Each of the first frame information structure corresponds to a first port multiplier port number. The first port multiplier sends the first frame information structures that correspond to the first port multiplier port numbers, respectively, to a first downstream port of the first port multiplier according to first port multiplier port number. The second port multiplier is configured to send the first frame information structures that are sent to the first downstream port to a plurality of second downstream ports of the second port multiplier, respectively. An operation method is also provided.

Abstract: An electronic device comprising a mainboard and a device is provided. The mainboard includes a first storage circuit, a CPU circuit and a data transmission interface circuit. The first storage circuit is configured to store a first firmware code of a basic input/output system, the CPU circuit is coupled to the first storage circuit, the CPU circuit is configured to execute the first firmware code to run the basic input/output system, and the data transmission interface circuit is coupled to the CPU circuit. The device is coupled to the data transmission interface circuit of the mainboard for providing a device function to the CPU circuit via the data transmission interface circuit. The device includes a controller, the controller includes a second storage circuit, a microcontroller and a suspend power register. An operation method of the electronic device is also provided.

Abstract: A data transmission method includes: determining a sum of first service proportions and a sum of second service proportions according to a first transmission rate of at least one first device, a second transmission rate of at least one second device, and a maximum bandwidth of a host transmission interface; determining at least one first service proportion of the first device according to the sum of the first service proportions, and determining at least one second service proportion of the second device according to the sum of the second service proportions; and transmitting at least one package of first transmission data of the first device and at least one package of second transmission data of the second device to a host via the host transmission interface according to the first service proportion and the second service proportion.

Abstract: An electronic device and a method for loading a program code thereof are disclosed herein. The electronic device includes a first controller, a second controller, a flash memory and a transmission interface. The flash memory is electrically connected to the first controller and stores a first program code corresponding to the first controller and a second program code corresponding to the second controller. The transmission interface is electrically connected between the first controller and the second controller. The first controller establishes a connection with the second controller via the transmission interface, and checks whether the second program code is valid. When the second program code is valid, the first controller loads the second program code to the second controller, so as to make the second controller execute the second program code.

Abstract: An electronic device comprising a mainboard and a device is provided. The mainboard includes a first storage circuit, a CPU circuit and a data transmission interface circuit. The first storage circuit is configured to store a first firmware code of a basic input/output system, the CPU circuit is coupled to the first storage circuit, the CPU circuit is configured to execute the first firmware code to run the basic input/output system, and the data transmission interface circuit is coupled to the CPU circuit. The device is coupled to the data transmission interface circuit of the mainboard for providing a device function to the CPU circuit via the data transmission interface circuit. The device includes a controller, the controller includes a second storage circuit, a microcontroller and a suspend power register. An operation method of the electronic device is also provided.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system. The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk. The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command.