Patents Assigned to ASTEC America, Inc.
  • Patent number: 6804788
    Abstract: A pulse width modulation controlling circuit for a power supply and method for controlling a switchmode power supply in a computer is disclosed. The present invention accomplishes control over the switching of the power supply by coarsely and then finely adjusting a time-length signal.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 12, 2004
    Assignee: ASTEC America, Inc.
    Inventors: Vadim Lubomirsky, Chen Wing Ling
  • Patent number: 5770023
    Abstract: An asymmetric bipolar plasma etching process is employed for etching a workpiece positioned within a plasma chamber, to prepare the workpiece for a subsequent coating process. The etching process involves applying a negative high voltage to the workpiece, relative to an anode portion of the chamber. Pulses of a positive voltage are applied to the workpiece at a predetermined pulse width and a predetermined level relative to the anode, so that the applied voltage appears as a train of asymmetric bipolar pulses. The waveform has a major negative-going portion and a minor positive-going portion. The negative-going portion can have a voltage of minus 300 to minus 4,000 volts, and the positive-going pulses can have a voltage of plus 50 to plus 300 volts, and a typical pulse width between about 0.25 and 3 microseconds. The etching process can be followed by a sputter coating process in the same chamber. Another coating technique could also be used.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: June 23, 1998
    Assignee: ENI A Division of Astec America, Inc.
    Inventor: Jeff C. Sellers
  • Patent number: 5737169
    Abstract: A protective circuit for a power field effect transistor, e.g., a power MOSFET, employs a diode-switched pickup circuit, a threshold detector, and a timer. The pickup circuit includes a resistor and diode in series, with the diode connected with the MOSFET drain electrode and the resistor connected with the gate driver for the MOSFET gate electrode. A pickup voltage V.sub.1 appears at the junction of the diode and resistor. When the MOSFET is conducting the pickup voltage is the sum of the channel voltage V.sub.ds-on and the diode forward voltage V.sub.f. When the MOSFET is biased OFF, the pickup voltage is zero. The threshold detector compares the pickup voltage with a reference voltage that is offset some predetermined amount from the source electrode voltage. When threshold circuit goes high, the timer circuit provides a time-out or inhibit signal to an inhibit input of the gate driver circuit. Under high load current or high temperature conditions, the drain-source voltage V.sub.
    Type: Grant
    Filed: February 28, 1996
    Date of Patent: April 7, 1998
    Assignee: ENI, A Division of Astec America, Inc.
    Inventor: Jeff C. Sellers
  • Patent number: 5627738
    Abstract: A soft start circuit for a high-power module permits trickle-charging of the capacitor bank prior to power switch actuation, and avoids large current surges or inrush at power up. Positive temperature coefficient thermistor devices, or PTCs are place in shunt across the switch elements or poles of the actuator or other power switch. In a power module that is powered by three-phase AC, the three power conductors are coupled through a three-pole contactor to AC inputs of a polyphase rectifier bridge, which has DC outputs coupled to the capacitor bank and to a load device, such as a high-power RF amplifier. The PTCs are connected, one per pole, in shunt across each pole of the contactor. Alternatively, metallized film capacitors can be employed in lieu of the PTCs.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: May 6, 1997
    Assignee: ENI, A Division of Astec America, Inc.
    Inventors: Vadim Lubomirsky, Jeff C. Sellers
  • Patent number: 5565737
    Abstract: An aliasing sampler probe for detecting plasma RF voltage and current employs a sampling signal with a sampling rate slower that the RF fundamental frequency selected to produce an aliasing waveform at an aliasing frequency that is several orders of magnitude below the RF fundamental frequency. In one embodiment, the RF power is applied at 13.56 MHz. and sampling pulses have a sampling rate of 2.732 MHz to produce replicas of the RF voltage and current waveforms at an aliasing frequency of about 100 KHz. The aliasing replicas preserve phase and harmonic information with an accuracy that is not available from other sampling techniques.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 15, 1996
    Assignee: ENI - a Division of Astec America, Inc.
    Inventor: Anthony R. A. Keane
  • Patent number: 5488331
    Abstract: A high-power radio-frequency amplifier acts on periodic pulses of RF energy. The bias is controlled for each of a bank of FETs or other amplifier devices that constitutes the main power stage. A sample of bias current is obtained during a blanking period on the front porch of the RF gating period. Quiescent drain current is measured, and stored on a sample/hold circuit. A digital signal processor provides bias values that are sent via a D/A converter to biasing circuits that add the bias levels to the input RF signal. If the bias current is above or below a desired level, the stored bias level is decreased or incremented respectively. A timing control circuit gates the sample/hold circuit and switches in advance of the biasing circuits. The timing control circuit also creates a blanking signal to apply to an attenuator to produce a null region during the first 100 microseconds of the gating signal.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: January 30, 1996
    Assignee: ENI, A Div. of Astec America, Inc.
    Inventors: Anthony R. A. Keane, Bart C. Vandebroek
  • Patent number: 5451907
    Abstract: A high-power radio-frequency amplifier act on periodic pulses of RF energy. The bias is controlled for each of a bank of FETs or other amplifier devices that constitutes the main power stage. A sample of bias current is obtained during a blanking period on the front porch of the RF gating period. Quiescent drain current is measured, and stored on a sample/hold circuit. A digital signal processor provides bias values that are sent via a D/A converter to biasing circuits that add the bias levels to the input RF signal. If the bias current is above or below a desired level, the stored bias level is decreased or incremented respectively. A timing control circuit gates the sample/hold circuit and switches in advance of the biasing circuits. The timing control circuit also creates a blanking signal to apply to an attenuator to produce a null region during the first 100 microseconds of the gating signal.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: September 19, 1995
    Assignee: ENI, Div. of Astec America, Inc.
    Inventors: Anthony R. A. Keane, Bart C. Vandebroek
  • Patent number: 5323329
    Abstract: An RF generator has an analog feedback circuit in combination with a digital levelling assist circuit to compensate for non-linearities in the power metering circuit that measures the RF output energy. The digital leveling assist circuit has a digitizer with inputs coupled to receive the measured power voltage supplied from the power metering circuit and a power demand voltage. The digitizer has outputs that provide digital representations of the measured power voltage and the power demand voltage to a digital control element that derives a digital correction factor based on these digital representations. A d/a converter coupled to the digital control element provides a correction voltage corresponding to this digital correction factor, and this is furnished to a summing circuit that combines the correction voltage with the power demand voltage and with a control voltage that is supplied by the analog feedback circuit.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: June 21, 1994
    Assignee: ENI, Div. of Astec America, Inc.
    Inventor: Anthony R. A. Keane
  • Patent number: 5291063
    Abstract: A high-power RF feedback resistor assembly includes a flat film resistor or other flat device mounted in thermal communication onto a bushing which is, in turn, mounted directly onto a cooling flange of an associated power transistor. A bushing has a vertical bolt hole through it to receive a threaded screw. The bushing can have a cutout beneath the flat vertical surface on which the resistor is mounted to provide clearance for a printed circuit board.
    Type: Grant
    Filed: December 23, 1991
    Date of Patent: March 1, 1994
    Assignee: ENI Div. of Astec America, Inc.
    Inventor: Gary C. Adishian
  • Patent number: 5249141
    Abstract: The present invention relates to the protection of a semiconductor active device from thermal breakdown without actually measuring the temperature of the semiconductor active device. Instead, the present invention measures the magnitude of the forward electrical signal generated by the active device and the reflected electrical signal resulting from the interaction of the forward electrical signal and a load. The thermal energy generated by the active device is a function of these electrical signals. The generated thermal energy is transferred out of the active device at a predetermined rate. The temperature of the active device is calculated as a function of the thermal energy generated by the active device and the amount of thermal energy transferred out of the active device. When the calculated temperature is above a predetermined value, the active device is shut off, thereby preventing further generation of thermal energy.
    Type: Grant
    Filed: October 24, 1990
    Date of Patent: September 28, 1993
    Assignee: Astec America, Inc.
    Inventors: Bart C. Vandebroek, Anthony R. Keane
  • Patent number: 5195045
    Abstract: An automatic impedance matching apparatus for matching an RF-signal generator to a load, such as a plasma etching chamber, is disclosed. The matching apparatus comprises a matching network having two variable impedance devices, a tune detector for detecting the condition of the impedance match between the RF-signal and the load, and a controller for modifying the values of the variable impedance components in response to the measured tune condition. The present invention disclosed improve reset and convergence unit and eliminates the need for the "dead-band" provided around the matching point found in prior art impedance matching controllers. Also disclosed is an improved adjustment unit for adjusting the variable impedance components which is faster and more stable than found in prior art controllers. Also disclosed is a normalization unit for normalizing the input detection siganls such that variations in turning performance due to variations in input power level from the source are substantially reduced.
    Type: Grant
    Filed: February 27, 1991
    Date of Patent: March 16, 1993
    Assignee: ASTEC America, Inc.
    Inventors: Anthony R. A. Keane, Steven E. Hauer
  • Patent number: 5189601
    Abstract: A dc-dc converter employs both half-bridge topology and current-mode switching control. The controller operates by sensing the current that flows through the transformer that is interposed between the node of two series switches and the node between the two split capacitors. The controller develops gating signals to close and open the switches based on the rise of current to a predetermined command level. A gate signal for the second switch, which is developed between actuations of the first switch, has its pulse width made equal to the period that the first switch was closed. This maintains a balanced voltage-time product, so that the series or split capacitors remain in balance. The controller can include a sample gating circuit with a comparator that receives the current sample signal and the command level. The track side signal which develops the gating pulse for the other switch can be developed with analog circuitry, i.e. by charging a capacitor, or else digitally, i.e. by clock pulse counting.
    Type: Grant
    Filed: November 18, 1991
    Date of Patent: February 23, 1993
    Assignee: ENI Div. of Astec America, Inc.
    Inventor: Jeff C. Sellers
  • Patent number: 5187457
    Abstract: A harmonic and subharmonic filter is coupled between a high power RF energy source and a non-linear RF load via a matching network, such as a plasma chamber. The filter passes high power RF energy in a band centered on a predetermined radio frequency, i.e., 13.56 MHz, but blocks and attenuates out-of-band energy at frequencies which are multiples of or fractions of the predetermined frequency. The harmonic and subharmonic filter comprises an input terminal, an output terminal, a series LC resonance path connected between the input and output terminals, and tuned to the predetermined radio frequency, a series resistive path formed of first and second resistors, and a parallel LC resonance path between the junction of the two resistors and ground.
    Type: Grant
    Filed: September 12, 1991
    Date of Patent: February 16, 1993
    Assignee: Eni Div. of Astec America, Inc.
    Inventors: Yogendra K. Chawla, Steven J. Smith