Abstract: The invention described herein includes a system, method, and computer program product for adding functionality to an application program. The invention includes a tool which can be used in conjunction with any of a plurality of application programs. The tool can be represented to a user by a tool icon on a desktop. After creating or opening a file or other object with an application program, the user can drag and drop a tool icon representing the tool into the application window. This allows the tool program to operate on the object. A windowing system event handler receives information from a user interface regarding the dragging and dropping of the tool icon. The fact that the tool icon has been dragged and dropped into the application window is reported by the windowing system event handler to a base module. The base module mediates communication between the tool program and the application program.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module controls a phase alignment between the processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: A method, system, and software for improved display of multiple media channels are disclosed herein. A system may be used to select, independent of direct user input, a subset of a plurality of media channels based on a user's viewing pattern. The system can include one or more media sources, a media processing system, and a display device, as well as a method for its use. The media processing system receives a plurality of media channels from the one or more media sources. One or more attributes associated with each media channel are compared with a user's viewing pattern determined independent of direct user input by the media processing system. A surf list is generated from the plurality of media channels, where the surf list includes a subset of the plurality of media channels having one or more attributes that are congruent with the user's viewing pattern. A portion, such as a still image, of each media channel in the surf list is output to an output device, such as a display device or storage device.

Abstract: The present invention is directed to a method, computer program product, and system for performing physics simulations on at least one graphics processor unit (GPU). The method includes the following steps. First, data representing physical attributes associated with at least one mesh are mapped into a plurality of memory arrays to set up of a linear system of equations that governs motion of the at least one mesh depicted in a scene. Then, computations are performed on the data in the plurality of memory arrays using at least one pixel processor to solve the linear system of equations for an instant of time, wherein modified data representing the solution to the linear system of equations for the instant of time are stored in the plurality of memory arrays.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: An embedded, programmable motion blur system and method is described herein. Embodiments include applying displacement on a vertex level and amplification on a primitive level within a graphics pipeline. Embodiments include receiving a plurality of vertices in a first component of a graphics processing unit (GPU), displacing each of the plurality of vertices, receiving a primitive that includes at least one of the displaced vertices in a second component of the GPU, and transforming the primitive. In one embodiment, transforming comprises at least one of translation, scaling, and rotation. Further included are generating a plurality of primitive samples over a time aperture, and outputting the plurality of primitive samples to further components of the GPU for further processing for display of the scene with motion blur.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: Embodiments of a method and system for intra-prediction in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which units of video data in a frame are to be processed using an intra-prediction operation. In an embodiment, intra-prediction is performed on a frame basis such that intra-prediction is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the intra-prediction such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

Abstract: An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

Abstract: The invention provides techniques for separating luma and chroma signal components in a composite SECAM video signal. During reception, the SECAM video signal is split into luma and chroma output. The amplitude of the chroma carrier is monitored during reception. If the chroma carrier amplitude is greater than a threshold, the value of the chroma output can be reduced. Also, if the chroma carrier amplitude is greater than another threshold, a portion of the chroma carrier can be added to the luma; or the trap band of the band-trap filter for extracting luma from the composite video can be reduced. The respective amount of the reduction in the chroma output and the increase in the luma output are independently determined but both may proportional to the magnitude of the deviation in the chroma carrier amplitude from the different thresholds.

Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor.

Abstract: A system and method for configuring an integrated circuit. Embodiments include a method for manufacturing an integrated circuit (IC), comprising associating configuration items of the integrated circuit with at least one fuse of at least one type of fuse, wherein a fuse comprises a bit field and a physical fuse, and configuring the integrated circuit by setting the at least one fuse to a value, comprising logically combining multiple fuse values to determine a particular configuration, wherein at least one of the fuse values is not alterable after manufacture of the IC.

Abstract: A video signal processing system including a digital signal processing (DSP) module, a digital offset module coupled to the DSP module, a gain module, and a digital to analog converter (DAC) coupled to the DSP module and to the gain module, wherein the DAC is configured to cause the gain module to provide multiple gain signals having predetermined first values to the DAC, cause, for each of the multiple gain signals, a digital input signal value to the DAC to be ramped up, determine, for each of the multiple gain signals, a lowest digital input signal value that causes an output voltage of the DAC to be at least as high as a reference voltage, and determine a second gain value that will cause the DAC to provide a desired DAC output voltage in response to the DAC receiving a reference DAC input value.