Abstract: A signal aliasing circuit that can be used especially to make a series interpolation cell of an interpolation analog-digital converter comprises two pairs of differential arms powered by one and the same current source connected to a first power supply terminal, each pair comprising two transistors, the transistors of one pair being parallel-connected with the transistors of the other pair. Each group of two parallel-connected transistors is connected by a respective common resistor to a second power supply terminal, the two outputs of the aliasing circuit being the combined collectors of the two groups of parallel-connected transistors. The disclosed device can be applied especially to converters whose architecture comprises what is known as a series interpolation part requiring high precision.

Abstract: A digital-analog current converter receives, at input, a succession of bits of a binary signal and delivers, at output, sampled by a clock signal, a positive or negative current depending on the state of the input bit. The converter comprises at least one circuit to control the build-up time of the output current of the converter, comprising a capacitor and a circuit to charge this capacitor controlled by the clock signal. The build-up time is controlled by the charging of a capacitor at a constant current up to a reference voltage. The circuit to control the build-up time of the output current may comprise at least two reference voltages, the capacitor being charged and then discharged between these two voltages. The build-up time of the output current is then the sum of the time taken to charge the capacitor and the time taken to discharge the capacitor.

Abstract: A sample-and-hold device comprises a sampling transistor (Qech) and a sampling capacitor (Cech), the sampling transistor being off in hold mode in order to prevent the discharging of the sampling capacitor and conductive in sampling mode to apply a voltage to the capacitor that is substantially equal to the voltage (Vech) at its base.