Abstract: A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

Abstract: A semiconductor device may include a semiconductor substrate having a front side and a back side opposite the front side, and a superlattice gettering layer on the front side of a semiconductor substrate. The superlattice gettering layer may include stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The device may further include an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, at least one semiconductor circuit in the active semiconductor layer, at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate. The superlattice gettering layer may further include gettered metal ions.

Abstract: A method for making a CMOS image sensor may include forming a superlattice on a semiconductor substrate having a first conductivity type, with the superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: A semiconductor processing method may include forming a superlattice gettering layer on a front side of a semiconductor substrate having a first thickness, epitaxially growing an active semiconductor layer on the superlattice gettering layer opposite the semiconductor substrate, forming at least one semiconductor device in the active semiconductor layer, and forming at least one metal interconnect layer on the active layer, and at least one metal through-via extending from the at least one metal interconnect layer into the semiconductor substrate. The method may further include thinning the semiconductor substrate from a back side thereof to a second thickness less than the first thickness, and thinning the semiconductor substrate. The superlattice gettering layer getters metal ions released by the forming of the at least one metal interconnect layer and at least one metal through-via, and thinning the substrate.

Abstract: A CMOS image sensor may include a first semiconductor chip including image sensor pixels and readout circuitry electrically connected thereto, and a second semiconductor chip coupled to the first chip in a stack and including image processing circuitry electrically connected to the readout circuitry. The processing circuitry may include a plurality of transistors each including spaced apart source and drain regions and a superlattice channel extending between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. Each transistor may further include a gate insulating layer on the superlattice channel and a gate electrode on the gate insulating layer.

Abstract: A semiconductor device may include a substrate, at least one memory array comprising a plurality of recessed channel array transistors (RCATs) on the substrate, and periphery circuitry adjacent the at least one memory array and including a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, a superlattice extending between the source and drain regions in the channel region, and a gate over the superlattice and between the source and drain regions. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A method for making a CMOS image sensor may include forming a plurality of laterally adjacent infrared (IR) photodiode structures on a semiconductor substrate having a first conductivity type. Forming each IR photodiode structure may include forming a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may have the first conductivity type. A semiconductor layer may be formed on the superlattice, along with a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well above the retrograde well having the first conductivity type.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent photodiodes formed in the substrate. Each photodiode may include a retrograde well extending downward into the substrate from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the second conductivity type, and a second well within the retrograde well having the first conductivity type. Each photodiode may further include first and second superlattices respectively overlying each of the first and second wells. Each of the first and second superlattices may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a superlattice on the semiconductor substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The image sensor may further include a plurality of laterally adjacent photodiodes on the superlattice. Each photodiode may include a semiconductor layer on the superlattice and having a first conductivity type dopant and with a lower dopant concentration than the semiconductor substrate, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: A method for making a semiconductor device may include forming at least one double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and forming a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the intrinsic semiconductor layer, and forming a second doped semiconductor layer on the second superlattice layer.

Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.

Abstract: A method for making a semiconductor device may include forming active circuitry on a substrate including differential transistor pairs, and forming threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors each includes spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Moreover, each of the channel regions may include a superlattice.

Abstract: A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.

Abstract: A semiconductor device including at least one double-barrier resonant tunneling diode (DBRTD) is provided. The at least one DBRTD may include a first doped semiconductor layer, and a first barrier layer on the first doped semiconductor layer and including a superlattice. The DBRTD may further include a first intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the first intrinsic semiconductor layer and also including the superlattice, a second intrinsic semiconductor layer on the second barrier layer, a third barrier layer on the second intrinsic semiconductor layer and also including the superlattice. A third intrinsic semiconductor layer may be on the third barrier layer, a fourth barrier layer may be on the third intrinsic semiconductor layer and also including the superlattice, a second doped semiconductor layer on the fourth barrier layer.

Abstract: A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.

Abstract: A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.

Abstract: A semiconductor device may include a substrate, active circuitry on the substrate and including differential transistor pairs, and threshold voltage test circuitry on the substrate. The threshold voltage test circuitry may include a pair of differential test transistors replicating the differential transistor pairs within the active circuitry, with each test transistor having a respective input and output, and at least one gain stage configured to amplify a difference between the outputs of the differential test transistors for measuring a threshold voltage thereof. The differential transistor pairs and the pair of differential test transistors may each include spaced apart source and drain regions, a channel region extending between the source and drain regions, and a gate overlying the channel region. Each of the channel regions may include a superlattice.

Abstract: A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate including a respective plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include epitaxially forming a semiconductor layer on the superlattice, and annealing the superlattice to form a buried insulating layer in which the at least some semiconductor atoms are no longer chemically bound together through the at least one non-semiconductor monolayer therebetween.

Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.