Abstract: A synchronization system aligns video signals without the use of a phase locked loop. One embodiment includes a delay line and a selection circuit. A clock signal with a desired frequency for a pixel clock is applied to the delay line to generate a series of delayed signals at taps on the delay line. When a transition in a horizontal sync signal occurs, the selection circuit senses delayed signals and selects a delayed signal having a transition aligned relative to the transition in the horizontal sync signal. This delayed signal is a pixel clock signal which is not subject to frequency fluctuation of a phase locked loop. Selecting a new delayed signal at each horizontal blanking period keeps the pixel clock for each line of video aligned to the horizontal sync signal.

Abstract: In a preferred embodiment, when full-motion video data is to be captured on a hard disk, a full-motion video memory on a video controller card has its addresses segmented into four groups, where each group can store one scaled-down frame (or field) of video data. The video memory is arranged to effectively act as a four-frame, first-in first-out (FIFO) buffer. The holding time of a single frame of data (i.e., four times the conventional holding time) in the video memory is sufficient to allow for the unpredictable variations in the hard drive timing so that frames are not arbitrarily dropped by worst case timing/accessing times of the hard drive. Hence, the average bandwidth and timing of the hard drive, rather than the instantaneous worst case bandwidth and timing of the hard drive, is used when designing the system.

Abstract: This method is most advantageous when an analog multiplexer is controlled to pass either analog graphics signals or analog motion video signals to a multimedia display screen. In the preferred embodiment, this method includes the steps of outputting a digital color key from a graphics memory buffer at a designated time and for a designated period and then converting this color key to an analog signal. This analog color key signal is then detected during this designated period and stored to obtain a stored color key value. The graphics memory is then controlled to output the graphics signals to be displayed on a multimedia screen. These graphics signals include a digital color key for controlling a multiplexer to display a motion video window on the multimedia screen in place of the color key. The outputted graphics signals are converted into analog signals, and these analog signals are compared to the stored color key value for detecting whether a color key is being outputted in the graphics data stream.

Abstract: A digital to analog converter is described for a multimedia system in which the magnitude of the analog output is controlled by signals applied to level select inputs of the digital to analog converter. Digital signals to be converted to an analog output are connected to a different set of inputs. This converter is advantageous for use in a display system where the brightness of the display may be independently controlled by the signals applied to the level select inputs. In this way, the digital information signals to be converted to an analog signal need not be modified to increase or decrease the brightness of the display.

Abstract: In the preferred embodiment, a method automatically aligning video data with a video window on a display screen in a multimedia system includes the steps of storing a selected color key in a graphics memory circuit, storing a chroma key in a motion video memory circuit, and simultaneously controlling the graphics memory circuit to output graphic signals and the motion video memory circuit to output video signals. The graphics signals are then compared to a stored color key to detect when the color key is transmitted within the graphics signals. When there is a match, a color key detection signal is generated. The outputted video signals are compared with a stored chroma key to detect when the chroma key is transmitted. When there is a match a chroma key detection signal is then generated.

Abstract: In a preferred embodiment, when full-motion video data is to be captured on a hard disk, a full-motion video memory on a video controller card has its addresses segmented into four groups, where each group can store one scaled-down frame (or field) of video data. The video memory is arranged to effectively act as a four-frame, first-in first-out (FIFO) buffer. The holding time of a single frame of data (i.e., four times the conventional holding time) in the video memory is sufficient to allow for the unpredictable variations in the hard drive timing so that frames are not arbitrarily dropped by worst case timing/accessing times of the hard drive. Hence, the average bandwidth and timing of the hard drive, rather than the instantaneous worst case bandwidth and timing of the hard drive, is used when designing the system.

Abstract: A single line buffer in a motion video card is used for both vertical reduction of the pixel image before storage in a video memory buffer and vertical expansion of the pixel image after being outputted by the video memory buffer. When the desired display size is smaller than the original pixel image size, then the line buffer is used by the input pipeline to reduce the image. When the desired display size is larger than the original pixel image size (or larger than the image stored in the memory buffer), then the line buffer is used by the output pipeline to enlarge the image.

Abstract: The bandwidth capability of a full-motion video buffer is prevented from being exceeded by automatically controlling the horizontal scaling of the incoming video data and the horizontal zooming or expansion of the outgoing display data to force the bandwidth of the video data to virtually match the bandwidth capability of the video buffer. In one embodiment, this automatic control of the horizontal scaling and zooming is performed in a dynamic fashion where a detector detects the dropping of any video bits caused by the bandwidth of the incoming video data exceeding the bandwidth capability of the video buffer. Upon detection of these dropped bits, the horizontal scaling of the incoming video data is incrementally reduced (and the horizontal zooming is proportionally increased) until the bandwidth of the incoming video data is at or below the maximum bandwidth capability of the memory buffer. In this way, the video buffer cannot be overdriven and no video data is lost.

Abstract: A multimedia video processor chip for a personal computer in employs a multi-port central cache memory to queue all the incoming data to be stored in a DRAM and all the outgoing data being retrieved from the DRAM. Such a cache memory is used in one of several modes in which the cache memory is partitioned by cache boundaries into different groups of storage areas. Each storage area of the cache is dedicated to storing data from a specific data source. The cache boundaries are chosen such that, for a given mode, the storage areas are optimized for worst case conditions for all data streams.