Abstract: A DC/DC converter includes an input to which an input current is supplied, an output at which an output current is provided, and a current control circuit coupled to the input and the output includes a unit that provides an instantaneous value signal proportional to the output current of the DC/DC converter with the aid of the input current, an internal input that supplies a reference signal, and a comparison device coupled to the unit that provides the instantaneous value signal and the internal input and comprises an internal output that provides a control signal dependent on a comparison of the instantaneous value signal with the reference signal, wherein the control signal adjusts the output current of the DC/DC converter.

Abstract: A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b).

Abstract: A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal.

Abstract: A sensor amplifier arrangement includes an amplifier having a signal input to receive a sensor signal and a signal output to provide an amplified sensor signal, and a feedback path that couples the signal output to the signal input and provides a feedback current that is an attenuated signal of the amplified sensor signal and is inverted with respect to the sensor signal.

Abstract: In the high-voltage transistor, which is suitable for an ESD-protection circuit, there is no doped well or at most a portion of a second well (3) of a second conductivity type opposite a first conductivity type under a contact region (4) for the drain between a first well (2) and a semiconductor material of the substrate (1), said semiconductor material being undoped or being doped for the first conductivity type. Said portion has a lower thickness than a thickness which would provide a good insulation of the first well from the substrate and which would provide a high-breakdown voltage.

Abstract: Through a main surface (10) of a semiconductor substrate (1) of a first type of conductivity, a doped well of a second type of conductivity is implanted to form a sensor region (3) extending perpendicularly to the main surface. The sensor region can be confined laterally by trenches (5) comprising an electrically insulating trench filling (6). The bottom of the sensor region is insulated by a pn-junction (20). Contacts (4) are applied to the main surface and provided for the application of an operation voltage and the measurement of a Hall voltage.

Abstract: A power source arrangement comprises a controlled and clocked operated power source, that power source providing an output voltage out of a plurality of output voltages in response to a first multiplication factor. One or more regulated current sources are connected to the controlled and clocked operated power source to provide an output current to respective loads. Each of the one or more regulated current sources is adapted to provide a first indication signal upon a regulated operation of the respective current source. The power source arrangement further comprises a dummy power source as well as a dummy current source connected to the dummy power source. The dummy current source receives a load signal corresponding to a voltage drop over the loads connected to the one or more regulated current sources and provides a second indication signal in response thereto.

Abstract: A filtering arrangement comprises a reference voltage input (1) and a compensation current arrangement (10) coupled to the reference voltage input (1) and configured to provide a control current at a current output (2) as a function of a voltage at the reference voltage input (1). The filtering arrangement also comprises a first and a second current source (20, 30) each having a control input (4, 5) coupled to the current output (2), a first and a second filter input (7, 8), and a first transistor (T1) and a second transistor (T2). The first transistor (T1) has a first connection (T11), a second connection (T12) and a control connection (T1c), where its first connection (T11) is coupled to the first current source (20) and its second connection (T12) is coupled to the first filter input (7) through a first resistor (R1).

Abstract: A semiconductor body (1) comprises a connecting lead (21) for contacting a semiconductor area (2). The conductivity S per unit length of the connecting lead (21) changes from a first value SW to a second value S0. The semiconductor area (2) is electrically conductively connected to the connecting lead (21).

Abstract: A method, in which a first isolating trench, filled with a dielectric material, and a second conducting trench, filled with an electrically conductive material, can be produced. To this end, the first and second trenches are etched with different trench widths, so that the first trench is filled completely with the dielectric material after a deposition of a dielectric layer over the entire surface with the edges covered, whereas the wider second trench is covered by the dielectric layer only on the inside walls. By anisotropic back-etching of the dielectric layer, the semiconductor substrate is exposed at the bottom of the second trench. Subsequently, the second trench is filled with an electrically conductive material and then represents a low-ohmic connection from the substrate surface to the buried structure located below the second trench.

Abstract: A voltage converter is provided in which a first terminal (A) and a second terminal (B) are provided, each coupled to a switching means, the switching means is coupled to respective terminals for connecting a first capacitor (C1), a second capacitor (C2) and a third capacitor (C3), and the voltage converter is configured for being operated in first and second modes of operation each comprising at least three phases, and in which the three capacitors (C1, C2, C3) are inserted in series connection (S) between the first terminal (A) and a reference potential terminal (10) in one phase, and in each of the two other phases a first path and a second path (P1, P2) are provided in each case in parallel connection with at least one of the three capacitors (C1, C2, C3) related to the second terminal (B).

Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.

Abstract: A well (2) doped for a conductivity type and provided as the sensor region is formed in a substrate (1) made of semiconductor material. Contact regions (4), arranged spaced apart from one another and doped for the same conductivity type as the well (2), are formed in a cover layer (3) that delimits the region with the conductivity type of the well. The contact areas (4) are electroconductively connected to the well (2) and provided for terminal contacts (6).

Abstract: A semiconductor body (1) comprises a first contact pad (2), a second contact pad (3), an integrated circuit (5) and an impedance (4). The integrated circuit (5) comprises a first terminal (6) which is coupled to the first contact pad (2) and a second terminal (7) which is coupled to the second contact pad (3). The impedance (4) additionally couples the first contact pad (2) to the second contact pad (3).

Abstract: In a measurement method, an array of magnetic field sensors (MS0-MS15) is provided, each emitting a sensor signal as a function of magnetic field intensity. A rotational value of a sector-wise magnetized magnetic source that is arranged movably with respect to the array is ascertained as a function of the emitted sensor signals. A set of sensor values is derived from the sensor signals. As a function of the ascertained rotational value, a number of sets of reference values is ascertained that corresponds to a number of predetermined positions of the magnetic source (MAG). The set of sensor values and the number of sets of reference values are compared to one another, and a position is selected from the number of predetermined positions as a function of the comparison.

Abstract: An amplitude of a carrier signal at an output of an impedance matching block is measured as a first amplitude value. A value of the signal amplitude at the output of the impedance matching block is calculated as a second amplitude value that a signal resulting from amplitude modulation with said modulation factor from said carrier signal should assume, said carrying signal having an amplitude with the first amplitude value. A setting of a transmitter is changed to decrease the carrier signal amplitude at the output of the impedance matching block. An amplitude of a new carrier signal at the output of the impedance matching block is measured as a new amplitude value. The transmitter setting keeps changing so many times until the new amplitude value is equal to or lower than said second amplitude value or within a predetermined tolerance range around said second amplitude value.

Abstract: A modulation arrangement comprises an input (E) for supplying a data signal (DS), a pre-modulator (VMod) that is coupled to the input (E) and features a clock pulse input (TEV) for supplying a pre-clock pulse (VT), a main modulator (HMod) that is coupled to the pre-modulator (VMod) on the input side and comprises a clock pulse input (TEH) for supplying a main clock pulse (HT), as well as an output for providing a modulated control signal (ST), and a switchable current source (Q, S) for providing a current (IS) that is controlled by the modulated control signal (ST) at an output (A) of the modulation arrangement. Furthermore, a method for providing a modulated control signal is disclosed.

Abstract: A circuit arrangement for supplying energy, comprising: a first input adapted to receive a first voltage from a first terminal of a control component, a second input adapted to receive a second voltage from a second terminal of the control component, a first output adapted to receive output a control signal to a control terminal of the control component for controlling an energy supply of an electrical load; and a power determining arrangement, comprising a switched-capacitor arrangement having an input coupled to the first and the second input of the circuit arrangement and an output coupled to the first output of the circuit arrangement.

Abstract: A microcontroller comprises a microprocessor (1), a test interface (4) and an internal non-erasable memory (2). First control means (6) are provided which are able to activate and deactivate the test interface (4), and second control means (7) are provided which are able to activate and deactivate the internal non-erasable memory (2). The microprocessor (1) of the microcontroller comprises control outputs (101) which are connected with the first and second control means (6, 7). With appropriate timing of activation and deactivation of the test interface (4) and the internal non-erasable memory (2), the microcontroller offers the possibility of preventing an unauthorized access to contents of the internal non-erasable memory (2) without limiting the usability of the test interface (4) for the development of application programs.

Abstract: A circuit arrangement for controlling a segmented LED backlight in particular, comprises a generator (50) with a first input (10) to be supplied with a synchronizing signal (SYNC) that comprises image frequency information and/or line frequency information of a display unit, a second input (20) to be supplied with a data signal (DATA) that comprises image information of the display unit, and with an output (30) for providing a modulated signal (MOD).