Patents Assigned to AVARY HOLDING (SHENZHEN) CO., LTD.
  • Patent number: 11792914
    Abstract: The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and first shielding columns. The core layer includes an accommodating space, and the accommodating space has an inner side wall. The first shielding ring wall is disposed in the accommodating space and covers the inner side wall, in which the first shielding ring wall surrounds the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The second circuit layer is disposed between the first insulating layer and the core layer. The first shielding columns are disposed in the first insulating layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 17, 2023
    Assignees: AVARY HOLDING (SHENZHEN) CO., LTD., HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO., LTD., GARUDA TECHNOLOGY CO., LTD.
    Inventors: Zhi-Hong Yang, Mao-Feng Hsu
  • Patent number: 11696391
    Abstract: A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 ?m. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: July 4, 2023
    Assignees: AVARY HOLDING (SHENZHEN) CO., LTD., HONGQISHENG PRECISION ELECTRONICS (QINHUANGDAO) CO., LTD., GARUDA TECHNOLOGY CO., LTD
    Inventors: Mao-Feng Hsu, Zhi-Hong Yang