Abstract: Disclosed is a dynamic range control circuit for determining when to allow an error correction circuit to correct data read from a sector of a disk data storage device. The circuit has two sets of registers used to count bytes of information within a sector. A first set of registers counts bytes as the sector is being read from the disk, and accumulates a count of a pre-data field and a count of a data field. These counts are then loaded into a second set of registers, along with a count indicating the length of the redundancy field within the sector. As correction is being performed, the second set of registers is decremented and the values in the registers used to set an in-range signal which allows a correction to the data field and prevents correction to the pre-data or redundancy fields.

Abstract: A high speed voltage controlled oscillator (VCO) providing for low sensitivity to the noise on the integrated circuit's (IC) power supply. The VCO circuit creates a supply voltage for a ring oscillator independent of the IC's power supply thereby controlling the frequency of operation independent of variations on the IC's power supply. A high speed CMOS level shifting circuit provides for converting outputs of the VCO with low logic level and varying frequencies to a signal with a full CMOS logic level and low duty cycle distortion.

Abstract: Disclosed is a disk controller having an interruptable error correction code circuit for accumulating a remainder during the writing to or reading from data storage media in a disk storage device. An ECC clock latches each bit of data into the circuit when data is being transferred. The ECC clock is controlled by an ECC clock control circuit that monitors sector data and redundancy data transfers to interrupt the ECC clock when sector data transfer is suspended before redundancy data transfer is started. The ECC clock is then allowed to resume after the suspension is complete. Sector data transfer is suspended while the read/write head of the data storage device is passing a defect in the media of the storage device. Since the ECC clock control circuit interrupts the ECC clock while data transfer is suspended, the remainder accumulation will be interrupted while the defect is being passed. While the remainder accumulation is interrupted, the circuit acts as if data is not being transferred during this time.