Abstract: A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

Abstract: A method for re-forming a complete ring network of a plurality of Bluetooth® speakers, after a speaker has left an original ring of speakers, the method including detecting that the speaker has left the ring, and reestablishing the ring without the departed speaker. The detection may include a timeout detection if the speaker left without notice, or include receiving notice that the speaker intends to leave.

Abstract: A fixture for calibrating an active noise canceling (ANC) earphone, the calibration fixture including an ear model and an acoustic path. The ear model is configured to support an ANC earphone and includes an ear canal extending from an outer end of the ear canal to an inner end of the ear canal. The acoustic path is external to the ear canal and extends from, at a first end of the acoustic path, the inner end of the ear canal of the ear model to an opposite, second end of the acoustic path. The acoustic path is configured to transmit a mechanical sound wave received from the inner end of the ear canal to a region external to the ear model and adjacent the outer end of the ear canal.

Abstract: An audio speaker system for a home theater including a number of microphones, a number of speakers, each speaker located at a different location in a room, and a processor electrically connected to the plurality of microphones and wirelessly connected to the plurality of speakers. The processor is configured to generate an audio signal to send to each speaker of the plurality of speakers, output audio from each speaker of the plurality of speakers based on the audio signal, receive the audio at each microphone from each speaker of the plurality of speakers, determine a location of each speaker relative to the plurality of microphones based on the received audio at each microphone, and assign an audio channel to each speaker based on the determined location.

Abstract: A speaker system includes a case, an audio input, speakers, an accelerometer, and a computer processor. The audio input is structured to receive a program audio signal from an audio device. The speakers are configured to play an audio output based on the program audio signal, the audio output causing a vibration of the case. The accelerometer is configured to detect the vibration of the case as well as a user tap on the case. The computer processor is configured to identify a user gesture that includes the tap on the case, to identify the tap apart from the case vibration by processing the detected vibration of the case and the detected user tap on the case based on information from the program audio signal to separate the detected user tap from the detected vibration, and to commence a particular function associated with the user gesture.

Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digi

Abstract: Disclosed is a signal processor for headphone off-ear detection. The signal processor includes an audio output to transmit an audio signal toward a headphone speaker in a headphone cup. The signal processor also includes a feedback (FB) microphone input to receive a FB signal from a FB microphone in the headphone cup. The signal processor also includes an off-ear detection (OED) signal processor to determine an audio frequency response of the FB signal over an OED frame as a received frequency response. The OED processor also determines an audio frequency response of the audio signal times an off-ear transfer function between the headphone speaker and the FB microphone as an ideal off-ear response. A difference metric si generated comparing the received frequency response to the ideal off-ear frequency response. The difference metric is employed to detect when the headphone cup is disengaged from an ear.

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

Abstract: A system for detecting and capturing voice commands, the system comprising a voice-activity detector (VAD) configured to receive a VAD-received digital-audio signal; determine the amplitude of the VAD-received digital-audio signal; compare the amplitude of the VAD-received digital-audio signal to a first threshold and to a second threshold; withhold a VAD interrupt signal when the amplitude of the VAD-received digital-audio signal does not exceed the first threshold or the second threshold; generate the VAD interrupt signal when the amplitude of the VAD-received digital-audio signal exceeds the first threshold and the second threshold; and perform spectral analysis of the VAD-received digital-audio signal when the amplitude of the VAD-received digital-audio signal is between the first threshold and the second threshold.

Abstract: An audio system can include an analog portion having multiple input sensors and an output device, a first digital portion running at a first rate and having a first processor that is electrically coupled with the input sensors and the output device, and a second digital portion running at a second rate that is higher than the first rate and having a second processor that is electrically coupled with the first processor.

Abstract: The disclosure includes a headset comprising one or more earphones including one or more sensing components. The headset also includes one or more voice microphones to record a voice signal for voice transmission. The headset also includes a signal processor coupled to the earphones and the voice microphones. The signal processor is configured to employ the sensing components to determine a wearing position of the headset. The signal processor then selects a signal model for noise cancellation. The signal model is selected from a plurality of signal models based on the determined wearing position. The signal processor also applies the selected signal model to mitigate noise from the voice signal prior to voice transmission.

Abstract: The disclosure includes an acoustic processing network comprising a Digital Signal Processor (DSP) operating at a first frequency and a Real-Time Acoustic Processor (RAP) operating at a second frequency higher than the first frequency. The DSP receives a noise signal from at least one microphone. The DSP then generates a noise filter based on the noise signal. The RAP receives the noise signal from the microphone and the noise filter from the DSP. The RAP then generates an anti-noise signal based on the noise signal and the noise filter for use in Active Noise Cancellation (ANC).

Abstract: The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

Abstract: A start-up circuit for a bandgap reference voltage generator circuit, including a first native transistor with a drain connected to a supply voltage of the bandgap reference voltage generator circuit and a source connected to a gate of the first native transistor; a low voltage transistor with a source connected to ground, a drain connected to the source of the first native transistor, and a gate connected to a resistor; a second native transistor with a source connected to the resistor, a gate connected to the source of the first native transistor; a high voltage transistor with a drain connected to a drain of the second native transistor and a source connected to the supply voltage; and a transistor with a gate connected to the gate of the first high voltage transistor and a drain which provides a start-up current for the bandgap reference voltage generator circuit.

Abstract: The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

Abstract: A Class G amplifier system including a processing unit configured to receive an input signal and output a delayed processed input signal, a class G amplifier configured to receive the delayed processed input signal, and a power supply. The power supply includes a regulator configured to operate in a plurality of configurations, each configuration outputs a different supply voltage to the class G amplifier and a control circuit configured to receive the input signal and determine the supply voltage required from the regulator when the delayed processed input signal is received at the class G amplifier, and output a signal to the regulator to indicate the required configuration for the required supply voltage.

Abstract: Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.