Patents Assigned to Avolare 2, LLC
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Publication number: 20120126311Abstract: A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout.Type: ApplicationFiled: October 11, 2011Publication date: May 24, 2012Applicant: AVOLARE 2, LLCInventor: John P. Snyder
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Patent number: 8154025Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.Type: GrantFiled: September 18, 2009Date of Patent: April 10, 2012Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Publication number: 20120056250Abstract: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.Type: ApplicationFiled: November 14, 2011Publication date: March 8, 2012Applicant: AVOLARE 2, LLCInventors: John P. Snyder, John M. Larson
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Patent number: 8084342Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.Type: GrantFiled: October 20, 2010Date of Patent: December 27, 2011Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Patent number: 8058167Abstract: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.Type: GrantFiled: September 28, 2009Date of Patent: November 15, 2011Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Patent number: 8022459Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.Type: GrantFiled: March 8, 2010Date of Patent: September 20, 2011Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Publication number: 20110175160Abstract: A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: AVOLARE 2, LLCInventor: John P. Snyder
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Patent number: 7939902Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.Type: GrantFiled: September 25, 2009Date of Patent: May 10, 2011Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Publication number: 20110034016Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.Type: ApplicationFiled: October 20, 2010Publication date: February 10, 2011Applicant: AVOLARE 2, LLCInventors: John P. Snyder, John M. Larson
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Patent number: 7821075Abstract: A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.Type: GrantFiled: October 12, 2006Date of Patent: October 26, 2010Assignee: Avolare 2, LLCInventors: John P. Snyder, John M. Larson
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Publication number: 20100213556Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.Type: ApplicationFiled: March 8, 2010Publication date: August 26, 2010Applicant: AVOLARE 2, LLCInventors: John P. Snyder, John M. Larson
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Patent number: 7674680Abstract: The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.Type: GrantFiled: October 5, 2004Date of Patent: March 9, 2010Assignee: Avolare 2, LLCInventors: John P. Snyder, John P. Larson
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Publication number: 20100032771Abstract: A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.Type: ApplicationFiled: October 16, 2009Publication date: February 11, 2010Applicant: AVOLARE 2, LLCInventor: John P. Snyder
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Publication number: 20100025774Abstract: A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a new distribution of mobile charge carriers in the bulk region of the semiconductor substrate, which improves device and circuit performance by lowering gate capacitance, improving effective carrier mobility ?, reducing noise, reducing gate insulator leakage, reducing hot carrier effect and improving reliability.Type: ApplicationFiled: October 13, 2009Publication date: February 4, 2010Applicant: AVOLARE 2, LLCInventors: John P. Snyder, John M. Larson
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Publication number: 20100013014Abstract: The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.Type: ApplicationFiled: September 25, 2009Publication date: January 21, 2010Applicant: AVOLARE 2, LLCInventors: John P. Snyder, John M. Larson
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Publication number: 20100015802Abstract: A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.Type: ApplicationFiled: September 28, 2009Publication date: January 21, 2010Applicant: AVOLARE 2, LLCInventors: John P. Snyder, John M. Larson
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Publication number: 20100013015Abstract: A Schottky barrier MOSFET (SB-MOS) device and a method of manufacturing having a silicon-on-nothing (SON) architecture in a channel region are provided. More specifically, metal source/drain SB-MOS devices are provided in combination with a channel structure comprising a semiconductor channel region such as silicon isolated from a bulk substrate by an SON dielectric layer. In one embodiment, the SON dielectric layer has a triple stack structure comprising oxide on nitride on oxide, which is in contact with the underlying semiconductor substrate.Type: ApplicationFiled: September 29, 2009Publication date: January 21, 2010Applicant: AVOLARE 2, LLCInventor: John P. Snyder
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Publication number: 20100006949Abstract: A CMOS device and method of fabrication are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a CMOS device and CMOS integrated circuits, to eliminate the requirement for halo/pocket implants, shallow source/drain extensions to control short channel effects, well implant steps, and complex device isolation steps. Additionally, the present invention eliminates the parasitic bipolar gain associated with CMOS device operation, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art. The present invention, in one embodiment, uses a silicide exclusion mask process to form the dual silicide Schottky barrier source and/or drain contact for the complimentary PMOS and NMOS devices forming the CMOS device.Type: ApplicationFiled: September 18, 2009Publication date: January 14, 2010Applicant: AVOLARE 2, LLCInventors: John P. Snyder, John M. Larson