Patents Assigned to Azanda Network Devices, Inc.
  • Publication number: 20040228355
    Abstract: A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.
    Type: Application
    Filed: June 15, 2004
    Publication date: November 18, 2004
    Applicant: Azanda Network Devices, Inc.
    Inventors: Bidyut Parruck, Joseph A. Nguyen, Chulanur Ramakrishnan
  • Patent number: 6810039
    Abstract: A processor-based architecture having a processor for facilitating transmission between an ATM port, a first packet port, and a second packet port. The processor-based architecture includes random access memory and a processor coupled to the random access memory and configured to receive ATM cells from the ATM port and first packets from the first packet port and for outputting second packets containing information from both the ATM cells and the first packets on the second packet port. The processor-based architecture includes segmentation-and-reassembly to facilitate bi-directional packet-to-ATM translation functionality. In one embodiment, the processor-based architecture is implemented on a single card and includes dynamic traffic management between ATM and packet traffic.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 26, 2004
    Assignee: Azanda Network Devices, Inc.
    Inventors: Bidyut Parruck, Joseph A. Nguyen, Chulanur Ramakrishnan
  • Patent number: 6751224
    Abstract: An integrated ATM/packet segmentation-and-reassembly engine for handling both packet and ATM input data and outputting packets containing information from both the packet and ATM input data. The integrated ATM/packet segmentation-and-reassembly engine is also configured for receiving packets containing information destined for transmission as ATM cells and information destined for transmission as packets, perform the segregation function and segmentation function on the information destined for transmission as ATM cells in order to output both ATM cells and packets. Architecture includes the ability to output both ATM cells and packets on a single optical fiber.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: June 15, 2004
    Assignee: Azanda Network Devices, Inc.
    Inventors: Bidyut Parruck, Joseph A. Nguyen, Chulanur Ramakrishnan
  • Patent number: 6751214
    Abstract: A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: June 15, 2004
    Assignee: Azanda Network Devices, Inc.
    Inventors: Bidyut Parruck, Joseph A. Nguyen, Chulanur Ramakrishnan