Abstract: Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous ordering operation.

Abstract: Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include application code. The block of code does not necessarily indicate that the block of code should be speculatively executed.

Abstract: Executing a set of one or more instructions atomically is disclosed. Executing includes determining whether speculatively executing the instructions is advised based at least in part on dynamic information associated with synchronization data and speculatively executing the instructions when it is determined that speculatively executing the instructions is advised.

Abstract: A technique is disclosed for redirecting information in a segmented virtual machine. The technique includes sending information to a shell VM and redirecting the information to bypass the shell VM. A technique for evaluating whether to redirect information may include sending a discovery packet, receiving a reply to the discovery packet; and determining whether a switch is capable of stitching based on the reply. A technique for responding to a discovery packet may include receiving the discovery packet at a switch and sending a response indicating a capability of the switch.

Abstract: An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.

Abstract: A technique for executing a segmented virtual machine (VM) is disclosed. A plurality of core VM's are implemented in a common core space. Each core VM is associated with a shell VM. Resources of the core space are allocated among the core VM's. A core VM is associated with a shell VM configured to perform shell VM functions and communicate with the core VM. VM internal execution functionality is performed on the core VM. The shell VM may be bypassed to communicate with an external application.

Abstract: A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a garbage collection barrier instruction and a subsequent instruction that immediately follows the garbage collection barrier instruction; wherein the processor is configured to execute the garbage collection barrier instruction, including by: evaluating a memory reference to determine a condition associated with the garbage collection barrier instruction; and in the event that the condition is met, while maintaining the same privilege level, saving information that is based at least in part on the current value of a program counter, and setting the program counter to correspond to a target location that is other than the location of the subsequent instruction.

Abstract: A technique for executing a segmented virtual machine (VM) is disclosed. A plurality of core VM's is implemented in a plurality of core spaces. Each core VM is associated with one of a plurality of shell VM's. Resources of the core spaces are allocated among the core VM's.

Abstract: Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an array element that corresponds to the index. Accessing memory in the array further includes, in the event that the index is within a valid range, performing a second instruction to access the array element, the access being based at least in part on the memory address determined by the first instruction.

Abstract: A computer system includes a memory and a processor coupled with the memory, configured to assign to each of a plurality of processes a corresponding amount of committed memory from a memory pool, the memory pool including committed memory and uncommitted memory; and dynamically allocate an additional amount of memory required by one of the plurality of processes from the uncommitted memory in the memory pool. Managing memory includes assigning to each of a plurality of processes a corresponding amount of committed memory from a memory pool, the memory pool including committed memory and uncommitted memory; and dynamically allocating an additional amount of memory required by one of the plurality of processes from the uncommitted memory in the memory pool.

Abstract: Executing an ordering operation is disclosed. A store operation associated with storing a value into a portion of a memory is initiated. An ordering operation to ensure that the store operation, but not necessarily all store operations, are completed is executed.

Abstract: A self-checking test generator program creates a self-checking test program that can test a device under test (DUT). The self-checking test generator selects instructions for a test. Selected instructions are executed on a software DUT model to generate results that can be self-checked by other instructions such as compare and branch instructions. The software DUT model has fuzzy models and unknown models for blocks in the DUT. Fuzzy models generate expected outputs for a block of the DUT. Fuzzy models may propagate unknown data from their inputs to their outputs. Unknown models do not predict expected outputs. Instead, unknown models always output unknown (X). Over time, as more of the DUT logic is modeled, unknown models may be replaced with fuzzy models.

Abstract: Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, transferring a first selected amount of data from the interface buffer to a shell VM buffer, transferring a second selected amount of data from the shell VM buffer to a core VM buffer, and providing portions of the data from the core VM buffer to the application in response to read requests from the application.

Abstract: A method, system, and computer program product for managing a heap of memory allocated to a program being executed on a data processing system is disclosed. A limited amount of memory is allocated to a program being executed by a mutator on a data processing system. The memory comprises memory objects. The disclosed method identifies memory objects, which are allocated to the program but are not referenced anymore. These dead memory objects are freed and made available for further allocation in the program. The memory objects that are still referenced are organized in compact contiguous blocks. Thus, the disclosed method recycles memory allocated to the program. The disclosed method is executed iteratively and concurrently with the execution of the program. The disclosed method does not interfere with program execution. Amount of memory required is specified before the commencement of the disclosed method and the same amount is freed without any surplus.

Abstract: A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.

Abstract: A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

Abstract: Accessing data comprises executing a set of computer instructions in a first environment, wherein the first environment has limited addressing capability to address memory up to a size limit, specifying a set of data in a memory space of a second environment, wherein the memory space has a size that exceeds the size limit, and accessing the set of data from the first environment using the limited addressing capability.

Abstract: Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand to provide a shifted, sign-extended operand, and adding the shifted, sign-extended operand to the second operand. The second operand has a different bit length than the first operand.

Abstract: A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

Abstract: A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the shared memory system, marking addresses in the shared memory system that have been operated on speculatively as being in a speculative state, and exiting the speculative mode, wherein exiting the speculative mode includes marking the addresses in the shared memory system that have been operated on as being in a non-speculative state.