Abstract: In a first aspect, a removable visual indication structure is disclosed. The removable visual indication structure includes a removable connection portion and a visual indication portion coupled to the removable connection portion wherein the visual indication structure can be removably attached to a printed circuit board. In a second aspect, a printed circuit board system is disclosed. The system includes a printed circuit board, at least one pin coupled to the printed circuit board, and at least one removable visual indication structure coupled to the at least one pin. In yet a third aspect, a method for fabricating a removable visual indication structure is disclosed. The method includes providing at least one visual indicator, providing a removable connector adapted to be coupled to the printed circuit board, and coupling the at least one visual indicator to the removable connector.

Abstract: A method and system for controlling data in a computer system when the computer system loses power is disclosed. The method and system comprises activating a plurality of super capacitors to supply power to the computing engine based upon power being removed from the computer system and reconfiguring the data in the computing engine. Through the use of a system and method, large amounts of newly written and modified data can be stored from the volatile memory to the non-volatile memory in the event of a sudden external system power loss. The system and method allows data to be rapidly and irretrievably erased from the non-volatile memory automatically, in the event of a sudden loss of external power, or manually. This capability consumes minimal space and weight and is implemented in an affordable manner.

Abstract: A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical block address (PBA) of the flash memory allocated to the logical address, and a cache valid bit and a cache index. When the cache valid bit is set, the data is read or written to a line in the cache pointed to by the cache index. A separate cache tag RAM is not needed. When the cache valid bit is cleared, the data is read from the flash memory block pointed to by the PBA. Two write count values are stored with the PBA in the table entry. A total-write count indicates a total number of writes to the flash block since manufacture. An incremental-write count indicates the number of writes since the last wear-leveling operation that moved the block.

Abstract: A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code when stored in the flash-memory chips. A DRAM cache stores the pages of data as enlarged pages with the overhead bytes, even though the enlarged pages are not aligned to a power of 2. When an enlarged page is read out of a flash-memory chip, its ECC code is immediately checked and the ECC code in the overhead bytes is replaced with a syndrome code and stored in the DRAM cache. A local processor for the flash-memory system then reads the syndrome code in the overhead bytes and repairs any error using repair information in the syndrome. The overhead bytes are stripped off when pages are transferred from the DRAM cache to a host.

Abstract: A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips.