Abstract: A parity bit memory simulator including a parity bit memory formed of a single bit memory of fixed address length, which replaces the single bit parity RAM of variable address length of conventional memory modules, is connected with its address signal line to the data bus of the memory module so that the parity bit memory provides and stores parity bits for the computer system without changing the circuit layout of the data memory or caring about the capacity of the memory module. A voltage level detector and a refreshing operation detector can be installed in the parity bit memory to improve an error detecting function of a dynamic random access memory module in the parity bit system.

Abstract: A new memory checker comprised of a parity checker (51), a bit storage (52), and a parity generator (53), and installed in the memory module (20) of a computer system (10) for checking data error, wherein the parity checker (51) receives the data bus and input parity signal from the computer system (10) to check out error from the data been fetched from the memory module (20) and then to provide an interrupt signal (43) to the computer system (10) upon the checking of an error.