Abstract: A fan control system applied to N fans inside a computer system is disclosed, comprising: a main microphone, a control circuitry, a wave generation circuitry and a number N of fan controllers. The control circuitry calculates a basic frequency value according to a temperature inside the computer system, and continuously updates a parameter by any known optimization algorithm according to a main audio signal from the main microphone. The wave generation circuitry generates N square waves according to the basic frequency value and the parameter. The N fan controllers respectively form and transmit N modulation signals to the N fans according to the N square waves and N tachometric signals from the N fans. The parameter is one of a frequency variation and a set of phase differences, and the N square waves have the same frequency.

Abstract: A hearing device is disclosed, comprising a main microphone, M auxiliary microphones, a transform circuit, a processor, a memory and a post-processing circuit. The transform circuit transforms first sample values in current frames of a main audio signal and M auxiliary audio signals from the microphones into a main and M auxiliary spectral representations. The memory includes instructions to be executed by the processor to perform operations comprising: performing ANC over the first sample values using an end-to-end neural network to generate second sample values; and, performing audio signal processing over the main and the M auxiliary spectral representations using the end-to-end neural network to generate a compensation mask. The post-processing circuit modifies the main spectral representation with the compensation mask to generate a compensated spectral representation, and generates an output audio signal according to the second sample values and the compensated spectral representation.

Abstract: An own voice suppression apparatus applicable to a hearing aid is disclosed. The own voice suppression apparatus comprises: an air conduction sensor, an own voice indication module and a suppression module. The air conduction sensor is configured to generate an audio signal. The own voice indication module is configured to generate an indication signal according to at least one of user's mouth vibration information and user's voice feature vector comparison result. The suppression module coupled to the air conduction sensor and the own voice indication module is configured to generate an own-voice-suppressed signal according to the indication signal and the audio signal.

Abstract: A voice event detection apparatus is disclosed. The apparatus comprises a vibration to digital converter and a computing unit. The vibration to digital converter is configured to convert an input audio signal into vibration data. The computing unit is configured to trigger a downstream module according to a sum of vibration counts of the vibration data for a number X of frames. In an embodiment, the voice event detection apparatus is capable of correctly distinguishing a wake phoneme from the input vibration data so as to trigger a downstream module of a computing system. Thus, the power consumption of the computing system is saved.

Abstract: There is provided a smart engine including a profile collector and a main processing module. The profile collector is configured to store a plurality of profiles, one or more suitable profiles being dynamically selected according to an instruction from a user or an automatic selector. The main processing module is connected to the profile collector and directly or indirectly connected to a sensor, and configured to perform a detailed analysis to determine detailed properties of features, objects, or scenes based on suitable sensor data from the sensor.

Abstract: An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.

Abstract: A speech enhancement apparatus is disclosed and comprises an adaptive noise cancellation circuit, a blending circuit, a noise suppressor and a control module. The ANC circuit filters a reference signal to generate a noise estimate and subtracts a noise estimate from a primary signal to generate a signal estimate based on a control signal. The blending circuit blends the primary signal and the signal estimate to produce a blended signal. The noise suppressor suppresses noise over the blended signal using a first trained model to generate an enhanced signal and a main spectral representation from a main microphone and M auxiliary spectral representations from M auxiliary microphones using (M+1) second trained models to generate a main score and M auxiliary scores. The ANC circuit, the noise suppressor and the trained models are well combined to maximize the performance of the speech enhancement apparatus.

Abstract: A processing apparatus applied in an artificial neuron is disclosed. The processing apparatus comprises a parser, a lookup array, a summing circuit and a MAC circuit. The parser parses one of M packets to extract a non-zero weight value from a header of the one packet, to identify a plurality of bit positions with a specified digit from a payload of the one packet, and to output the non-zero weight value and the bit positions in parallel. The lookup array contains N synapse values and is indexed by the bit positions in parallel to generate a plurality of match values. The summing circuit sums up the match values to generate a sum value. The MAC circuit generates a product of the non-zero weight value and the sum value, and generates an accumulate value based on the product and at least one previous accumulate value.

Abstract: A spread spectrum based audio frequency communication system at least includes a transmitting apparatus. The transmitting apparatus includes a first dot-product module, a summation module, a transmitting modulation module, a mixture module, a digital-to-analog converter, and a transmitter. The first dot-product module is configured to perform a dot-product of a first data and a first pseudo-noise code, and derive a first spreading data. The summation module is configured to sum up the first spreading data and a second spreading data to form a summed data. The transmitting modulation module is configured to vary a carrier signal with the summed data to form a modulated signal. The mixture module is configured to mix the modulated signal and an acoustic signal up to form a mixed signal. The digital-to-analog converter is configured to convert the mixed signal into acoustic waves. The transmitter transmits the acoustic waves.

Abstract: An acceleration apparatus applied in an artificial neuron is disclosed. The acceleration apparatus comprises an AND gate array, a first storage device, a second storage device and a multiply-accumulate (MAC) circuit. The AND gate array with plural AND gates receives a first bitmap and a second bitmap to generate an output bitmap. The first storage device stores a first payload and outputs a corresponding non-zero first element according to a first access address associated with a result of comparing the first bitmap with the output bitmap. The second storage device stores a second payload and outputs a corresponding non-zero second element according to a second access address associated with a result of comparing the second bitmap with the output bitmap. The MAC circuit calculates a dot product of two element sequences from the first storage device and the second storage device.

Abstract: A method for matrix by vector multiplication, applied in an artificial neural network system, is disclosed. The method comprises: compressing a plurality of weight values in a weight matrix and indices of an input vector into a compressed main stream; storing M sets of synapse values in M memory devices; and, performing reading and MAC operations according to the M sets of synapse values and the compressed main stream to obtain a number M of output vectors. The step of compressing comprises: dividing the weight matrix into a plurality of N×L blocks; converting entries of a target block and corresponding indices of the input vector into a working block and an index matrix; removing zero entries in the working block; shifting non-zero entries row-by-row to one of their left and right sides in the working block; and, respectively shifting corresponding entries in the index matrix.