Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.

Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: Methods, apparatuses, and systems are presented for switching between channels of encoded media data involving receiving encoded media data including reference frames and dependent frames for a plurality of channels, wherein each dependent frame refers to at least one reference frame. Frames associated with a first channel from the plurality of channels are decoded to generate a decoded signal for the first channel. While decoding frames associated with the first channel, data corresponding to at least one reference frame associated with a second channel from the plurality of channels are stored. In response to a control signal for switching from the first to the second channel, at least one dependent frame associated with the second channel is decoded by utilizing the stored data corresponding to the at least one reference frame associated with the second channel, to generate a decoded signal for the second channel.

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.

Abstract: An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.

Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.

Abstract: A system for high-speed access and recording includes a demodulator, a buffer memory, and a hard disk. During a write cycle, a content stream is stored in buffer memory and thereafter transferred to the demodulator. When the buffer memory reaches its storage capacity, its contents are transferred to the hard disk for storage. During a read cycle, contents from the hard disk are read and then stored in the buffer memory. The hard disk further includes includes a high-speed zone and a random-access zone, which are configured to operate in a high-speed mode, a random-access mode, and a buffer-cleaning mode.

Abstract: A system for optimizing bandwidth of a video-on-demand system is provided. According to one aspect of the system, upon receiving a request from a first subscriber for a program, the system delivers the program to the first subscriber via a first communication channel. Upon receiving a request from a second subscriber for the same program, the system delivers only a beginning portion of the program to the second subscriber via a second communication channel and at the same time records a remaining portion of the program from the first communication channel. At the appropriate time, the recorded remaining portion of the program are shown to the second subscriber.

Abstract: A system for providing multi-channel multi-mode QAM equalization and carrier recovery is provided. According to one exemplary embodiment, the system includes an equalization circuit and a carrier recovery circuit operating in a concurrent manner to provide equalization and carrier recovery. The equalization circuit and the carrier recovery circuit each have two operating modes, namely, an acquisition mode and a tracking mode. The carrier recovery circuit evaluates a phase detection error calculated based on signals obtained from the equalization circuit. Based on the evaluation of the phase detection error, the equalization circuit and the carrier recovery circuit are respectively directed to switch operating mode, if appropriate.

Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.

Abstract: A digital automatic gain control circuit is disclosed. The circuit includes a selector, a scaler, a detector, a gain adjustor and a controller. In one exemplary aspect, the selector receives an input signal having two components, namely, the in-phase (I) and quadrature (Q) components, in digital form. The selector then selects a subset of bits from each component based on a control signal provided by the controller. The two subsets are then forwarded to the scaler. The scaler then multiplies the two subsets respectively against a gain value to generate two multiplication results. A portion of each multiplication result is then provided as output by the scaler. The gain value and the subset selection are periodically adjusted in response to the scaler output. The adjustments with respect to the gain value and the subset selection are effectuated collectively by the detector, the gain adjustor and the controller.

Abstract: A system for providing jitter-free transmissions for demodulated data streams is disclosed. In one embodiment, the system includes a demodulator, a packet processor and a timing generator. The demodulator further includes a timing recovery circuit. Output signals from the timing recovery circuit and demodulated output signals from the demodulator are provided to the timing generator. Using these signals, the timing generator then generates an output timing signal. Demodulated data are provided to the packet processor as input. The demodulated data are then output by the packet processor under the control of the output timing signal from the timing generator.

Abstract: A method and circuitry for implementing digital multi-channel demodulation circuits. More particularly, embodiments of the present invention provide a digital multi-channel demodulator circuit. The demodulator includes a frequency-block down-converter that receives a multi-channel analog RF signal and shifts the multi-channel analog RF signal to a lower frequency band. An ADC receives the multi-channel analog RF signal from the frequency-block down-converter and converts the multi-channel analog RF signal to a multi-channel digital RF signal. A digital channel demultiplexer receives the multi-channel digital RF signal from the ADC and demultiplexes the multi-channel digital RF signal into separate digital RF channels.

Abstract: An improved multi-channel demodulator is provided. The improved demodulator includes an automatic gain control, a data buffer and a demodulation engine. Data from various RF channels are processed by the automatic gain control in order to keep the data at their respective constant levels. Output from the automatic gain control is passed to the data buffer for storage. Corresponding data from a selected channel is then processed by the demodulation engine. The improved demodulator is able to operate in any one of three operating modes, namely, a data processing mode, a channel switching mode and a waiting mode. In the data processing mode, the demodulation engine processes the channel data that is currently loaded into the demodulation engine. In the channel switching mode, the demodulation engine stores the current channel data into the data buffer and retrieves and loads channel data from another channel for processing.

Abstract: The system of a content head end of a distribution system includes a program multiplexer, a multi-channel modulating module, a channel multiplexer, a digital-to-analog converter and a frequency block-up converter, all arranged in a sequential configuration. Packets representing respective content programs are fed to the program multiplexer. The program multiplexer multiplexes the packets into an output queue. Packets from the output queue are then fed to the multi-channel modulating module. The multi-channel modulating module receives the packets and routes them to various modulators representing corresponding RF channels. The various modulators then modulate the respective packets to generate corresponding RF signals. These RF signals are then multiplexed by the channel multiplexer into a multi-channel RF signal. The multi-channel RF signal is then forwarded to the digital-to-analog converter for conversion into an analog, multi-channel RF signal.

Abstract: A system for implementing a base band compression scheme for a nonlinear multiplying up-converter for QPSK and OQPSK includes a bit combining module, a quadrant remap module, a look-up table (LUT) and a zoom adjust module. The bit combining module is configured to generate an address based on a number of symbols received as input data. Using the address provided by the bit combining module, the quadrant remap module remaps symbols from quadrants “2”, “3” and “4” to quadrant “1” and generates signals to look up corresponding output data from the LUT. The zoom adjust module generates a number of solutions corresponding to the input data using the corresponding output data retrieved from the LUT. The zoom adjust module is then used to select the best output from the solutions to provide a smooth output signal that does not have any discontinuities.

Abstract: A system for providing adaptive timing recovery is provided. In an exemplary embodiment, the system includes a fractional resampler, an error function module and a loop filter, arranged collectively to form a timing recovery loop. In an initial mode, the error function module compares the output of the fractional resampler with a reference signal to determine an error, if any. An error signal is generated accordingly based on the error. The error signal is then provided to the loop filter allowing the loop filter to generate a correction signal. The correction signal is provided to the fractional resampler to allow the fractional resampler to generate an output which minimizes the error. When the error function module determines that the error is within an acceptable range, i.e., a timing lock is achieved, the system goes into a steady mode. In the steady mode, the error function module is directed to execute at a slower rate.