Abstract: A segmented digital-to-analog converter includes a string DAC (210) and an interpolation DAC (211). The string DAC includes 2M series-connected string resistors (Ri) and 2M pairs of switches (Sia,b). The switch pairs couple a first (201) and second (202) conductor across each resister responsive to the MSB subword decoder (212). The interpolation DAC (211), responsive to the LSB subword decoder (215), connects an input of a plurality of differential stages to the first conductor (201) and second (202) conductor. Each differential stage includes a first transistor (QjA) and a second (QjB) transistor differentially coupled to a corresponding tail current source (In). The drains of the first (QjA) and second (QjB) transistors are connected to a first load device (QL1) and second (QL2) load device and the inverting and non-inverting inputs of the output amplifier (205) via third (203) and forth (204) conductors, respectively.

Abstract: A touch screen digitizing system includes a touch screen unit including a first resistive sheet with opposed x+ and x− terminals and a second resistive sheet with opposed y+ and y− terminals, and an ADC having first and second reference input terminals. A first switch is coupled between a first reference voltage and the x− terminal, and a second switch is coupled between the x+ terminal and a second reference voltage for energizing the first resistive sheet. A third switch is coupled between the first reference voltage and the y− terminal, and a fourth switch is coupled between the y+ terminal and the second reference voltage for energizing the second resistive sheet.

Abstract: A system for reducing sensitivity of an integrated circuit chopper-stabilized amplifier to intermodulation applies a pseudo-random sequence signal (11A) to an LSB of a first input of a first adder. An error feedback signal (18) is applied to a second input of the first adder and a first input of a second adder (16). A 1-bit quantization signal (&phgr;CH) is produced as an MSB of an output of the first adder and applied to an LSB of a second input of the second adder (16). An error signal (16A) representing the difference between the quantization signal (&phgr;CH) and the error feedback signal (18) is produced by the second adder (16). The error signal (16A) is delayed a predetermined amount to produce the error feedback signal (18), wherein energy of the quantization signal (&phgr;CH) is spread over a broad frequency spectrum between DC and FS/2. A pair of out-of-phase, non-overlapping chopping signals from the quantization signal (&phgr;CH).

Abstract: An LDO voltage regulator includes an error amplifier having a first input coupled to a first reference voltage, a second input receiving a feedback signal, and an output producing a first control signal. An output transistor has a gate, a drain coupled to an unregulated input voltage, and a source coupled to produce a regulated output voltage on an output conductor. A feedback circuit is coupled between the output conductor and a second reference voltage. An overvoltage comparator has a first input coupled to receive the first reference voltage and a second input coupled to respond to the feedback signal to produce a discharge control signal indicating occurrence of an output overvoltage of at least a predetermined magnitude to control a discharge transistor coupled between the output conductor and the second reference voltage. An output current sensing circuit produces a control current representative of the drain current of the output transistor.

Abstract: A linearization circuit includes a sensor circuit having a first terminal receiving an excitation voltage, and second and third terminals producing a sensor output voltage therebetween. A differential amplifier circuit produces a linearization current, and a scaling circuit operates to produce a scaled linearization current in response to the linearization current. A current direction switch circuit includes a fourth terminal receiving the scaled linearization current, a fifth terminal and conducting a correction current proportional to the linearization current, and a control terminal receiving a polarity control signal to determine the direction of flow of the correction current through the fifth terminal in response to the sensor output voltage.

Abstract: Capacitor voltage coefficient errors are reduced in a lossy integrator by providing oppositely oriented first and second feedback capacitors in a switched capacitor feedback circuit coupled between the output and a summing conductor connected to an inverting input of an operational amplifier. During a first clock signal, terminals of the first feedback capacitor are coupled to a reference voltage by closing first and second reset switches and the second feedback capacitor is coupled between the inverting input and the output conductor by closing first and second sampling switches. Then, during a second clock signal the terminals of the second feedback capacitor are coupled to the first reference voltage by closing third and fourth reset switches, and the second feedback capacitor is coupled between the inverting input and the output by closing third and fourth sampling switches.

Abstract: A self-calibrating digital-to-analog converter includes a delta-sigma modulator (25) receiving a digital input signal, an output producing a stream of digital pulses the density of which represents a value of the digital input signal, and an intermediate digital input port coupled to a digital summing element which is also coupled to an output of an integrator within the delta-sigma modulator. A 1-bit DAC converts the stream of digital pulses to an analog signal that is filtered to produce an analog output voltage. A 1-bit DAC converts the analog output signal to a digital feedback signal, and a successive approximation circuit produces a digital offset correction signal from the digital feedback signal and loads it into an offset register. An output port of the offset register is coupled to the intermediate digital input port to provide self-calibration of an offset error without skewing an input range of the digital input signal.

Abstract: A low drop out voltage regulator includes an error amplifier (12) having a first input coupled to a first reference voltage (VREF), a second input receiving a feedback signal, and an output (15) producing an output signal (VAMPOUT). An output transistor (18) has a gate, a drain coupled to an unregulated input voltage (VIN), and a source coupled to produce a regulated output voltage (VOUT) on an output conductor (19). A feedback circuit (20,22) is coupled between the output conductor (19) and a reference voltage (GND) to produce the feedback signal. A capacitor (16) is coupled between the output (15) of the error amplifier and the gate (17) of the output transistor (18). A servo amplifier (24) has a first input coupled to a second reference voltage (VVREF), a second input coupled to the output (15) of the error amplifier. A low current charge pump circuit (26B) supplies an output current into a supply voltage terminal of the servo amplifier.

Abstract: A digital-to-analog converter includes a resistive divider network including a plurality of series resistors of resistance R and a plurality of shunt resistors of resistance 2R' and a circuit for switching a shunt resistor of the resistive divider network in the digital-to-analog converter to either of first and second reference voltages. The switching circuit includes a first switch MOSFET coupling the low reference voltage to the shunt resistor, and a second switch MOSFET coupling the shunt resistor to the high reference voltage. First and second switch control circuits adjust the on resistances of the first and second switch MOSFETs to be proportional to the resistances of first and second reference resistors, which have the same temperature coefficient as the resistors of which the divider network is composed. The on resistance of each of the first and second switch MOSFETs is equal to R.sub.ONi, and the resistance 2R' is equal to 2R-R.sub.ONi. The on resistances do not need to be binarily scaled.

Abstract: A differential amplifier includes a rail-to-rail input stage including differentially coupled first (13) and second (14) P-channel input transistors, and differentially coupled third (17) and fourth (18) N-channel input transistors. The drains of the first and second input transistors are coupled to a first folded cascode circuit which includes first (25) and second (26) P-channel cascode transistors. The drains of the third and fourth input transistors are coupled to a second folded cascode circuit which includes third (36) and fourth (37) N-channel cascode transistors. An output stage includes a P-channel pull-up transistor and an N-channel pull-down transistor and a class AB bias circuit coupled between the gates thereof. The gates of the first (25) and third (36) cascode transistors are coupled to first and second reference voltages, respectively.

Abstract: In a delta-sigma type analog-to-digital converter, an offset varying during operation is removed, and a reduction in time required to generate a stable value after powering on the converter is achieved. A high pass filter is provided with a variable filter coefficient which can vary during operation. A filter coefficient controller supplies a coefficient control signal to the high pass filter to change the variable filter coefficient during operation, thereby altering the time constant of the high pass filter.

Abstract: An offset-compensated amplifier including an input stage (2) having a current source (10), first (11) and second (12) FETs each having a source connected to the current source, first (17) and second (18) input FETs each having a source connected to a drain of the first compensation FET (11), and third (19) and fourth (20) input FETs each having a source connected to a drain of the second compensation FET (12), a drain of each of the first (17) and third (19) input FETs being connected by a first output conductor (21) to a first load (23), and a drain of each of the second (18) and fourth (20) input FETs being connected by a second output conductor (22) to a second load (24), a gate of each of the first (17) and third (19) input FETs being connected to a first input (3A), a gate of each of the second (18) and fourth (20) FETs being connected to a second input (3B).

Abstract: A low noise differential amplifier includes a differential stage and first and second unbalanced differential feedback amplifiers. The differential stage includes first (13) and second (14) load devices coupled to first (11) and second (12) conductors, respectively, a resistor (RS), a first input transistor (Q1) having a first electrode coupled to the first conductor and a second electrode coupled by a third conductor (16) to a first terminal of the resistor (RS), and a second input transistor (Q2) having a first electrode coupled to the second conductor (12) and a second electrode coupled by a fourth conductor (17) to a second terminal of the resistor (RS). The first feedback amplifier (18) includes a third input transistor (Q5) coupled between the third conductor (16) and the first current source transistor (Q3). The first feedback amplifier (18) drives the control electrode of the first input transistor (Q1).

Abstract: A circuit for producing a stable CDAC reference voltage in a successive approximation analog-to-digital converter includes a circuit (27) producing an input reference voltage (VREFIN), and a buffer circuit (12) producing a stable reference voltage in response to the input reference voltage. The buffer circuit includes an amplifier (13) having a non-inverting input receiving the input reference voltage. A first buffer (13B) receives the output of the amplifier and produces output that is fed back to an inverting input of the amplifier. A second buffer (18) also receives the amplifier output. A first transistor switch (19) couples the output of the second buffer to a CDAC. A second transistor switch (29) couples the CDAC to ground. A third transistor switch (26) couples the first buffer to the CDAC. The first transistor switch (19) closes to cause an initial "coarse" charging of a first capacitance of the CDAC by the second buffer (18).

Abstract: Circuitry in an amplifier (1) provides both auto-zeroing of offset errors and finite gain compensation. The circuitry includes a differential main amplifier (3) and a differential auxiliary amplifier (13). During a first phase (.phi.1), a previously sampled input voltage is amplified by the main amplifier to produce an output voltage on a first capacitor (C3). A stored prior offset correction voltage stored on a second capacitor (C4A) is applied between the inputs of the auxiliary amplifier, an output of which is coupled to an auxiliary input of the main amplifier to auto-zero its offset voltage. During a second phase (.phi.2) the inputs of the main amplifier are short-circuited together, causing it to produce a voltage change on one terminal of the first capacitor (C3), the other terminal of which is switched from ground to one terminal of a second capacitor (C4). This stores updated offset correction voltage on the second capacitor (C4).

Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850.degree. C. As the substrate is heated to a temperature of 1050.degree. C. N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080.degree. C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080.degree. C.

Abstract: A bootstrap sample and hold circuit accurately acquires and holds values of a high frequency analog input signal, to avoid harmonic distortion of a signal representing the analog input signal in, for example, a pipeline ADC, includes a first sampling MOSFET coupling the analog input signal to a sampling capacitor. A bootstrap circuit includes a bootstrap capacitor. First and second MOSFETs couple the bootstrap capacitor between a first reference voltage and ground in response to pulses of a first clock signal. Third and fourth MOSFETs then couple the bootstrap capacitor between the gate and source of the sampling MOSFET in response to non-overlapping pulses of a second clock signal to apply a constant gate-to-source voltage to the sampling MOSFET, the gate-to-source voltage having a magnitude equal to the difference between a first reference voltage and ground during the pulses of the second clock signal.

Abstract: Curvature in a reference voltage produced by a switched capacitor band gap reference circuit is compensated by producing a first .DELTA.V.sub.BE voltage by causing first and second PTAT/R currents to flow through a first .DELTA.V.sub.BE -generating circuit. The first .DELTA.V.sub.BE voltage is applied to a first terminal of a first capacitor having a second terminal coupled to a summing conductor of an operational amplifier producing the reference voltage. A second .DELTA.V.sub.BE voltage is produced by causing a third PTAT/R current and a fourth current to flow through a second .DELTA.V.sub.BE -generating circuit. The second .DELTA.V.sub.BE voltage is applied to a first terminal or a second capacitor having a second terminal coupled to the summing conductor.

Abstract: A solenoid driver circuit includes an input terminal for receiving a solenoid actuation pulse, an output terminal for connection to a terminal of a solenoid coil, a pull-in current adjustment terminal, and a hold-in current duty cycle adjustment terminal. A pull-in current duration circuit includes a first input coupled to the input terminal, an output producing a pull-in current duration pulse, and a second input coupled to the pull-in current adjustment terminal. A hold-in current duty cycle control circuit includes a first input coupled to receive a triangular waveform signal, a second input coupled to the hold-in current duty cycle adjustment terminal, and a third input coupled to the output of the pull-in current duration circuit. An output transistor includes a control electrode coupled to an output terminal of the hold-in current duty cycle control circuit, and a current carrying terminal coupled to the output terminal.

Abstract: A programmable gain delta sigma analog-to-digital converter includes an analog input terminal receiving an analog input voltage, a charge summing conductor, an input capacitive switching circuit, and a feedback reference capacitive switching circuit coupled to the charge summing conductor. An integrator is coupled between the charge summing conductor and a comparator which supplies a stream of digital pulses to a digital filter that produces a digital number representing the analog input voltage. The feedback reference capacitive switching circuit includes a plurality of reference sampling capacitors, selectively coupling charge between a feedback reference voltage source and an integrating capacitor of the integration in response to a programmable gain control circuit so as to provide a selected gain for the analog-to-digital converter. The sampling rate of the capacitive switching circuits is adjusted proportionally to the selected gain to improve the dynamic range of the analog-to-digital converter.