Patents Assigned to Calos Fund Limited Liability Company
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Patent number: 8861611Abstract: A method of operation within an integrated circuit device having a plurality of processing lanes. A first sub-stream of data, having a variable length, is generated in a first one of the processing lanes. A second sub-stream of data, also having a variable length, is generated in a second one of the processing lanes. The first and second sub-streams are then output to form a single bitstream.Type: GrantFiled: August 15, 2008Date of Patent: October 14, 2014Assignee: Calos Fund Limited Liability CompanyInventors: Ujval J. Kapasi, Yipeng Liu, Dan Miller
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Patent number: 8786614Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.Type: GrantFiled: May 2, 2013Date of Patent: July 22, 2014Assignee: Calos Fund Limited Liability CompanyInventors: Donald James Curry, Ujval J. Kapasi
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Patent number: 8694757Abstract: Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory.Type: GrantFiled: August 15, 2008Date of Patent: April 8, 2014Assignee: Calos Fund Limited Liability CompanyInventors: Brucek Khailany, Mark Rygh, Jim Jian Lin, Udo Uebel
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Publication number: 20130241940Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.Type: ApplicationFiled: May 2, 2013Publication date: September 19, 2013Applicant: Calos Fund Limited Liability CompanyInventors: Donald James Curry, Ujval J. Kapasi
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Patent number: 8456480Abstract: In a single-instruction-multiple-data (SIMD) processor having multiple lanes, and local memory dedicated to each lane, a method of processing an image is disclosed. The method comprises mapping consecutive rasters of the image to consecutive lanes such that groups of consecutive rasters form image strips, and vertical stacks of strips comprise strip columns. Local memory allocates memory to the image strips. A sequence of functions is processed for execution on the SIMD processor in a pipeline implementation, such that the pipeline loops over portions of the image in multiple iterations, and intermediate data processed during the functions is stored in the local memory. Data associated with the image is traversed by first processing image strips from top to bottom in a left-most strip column, then progressing to each adjacent unprocessed strip column.Type: GrantFiled: January 13, 2010Date of Patent: June 4, 2013Assignee: Calos Fund Limited Liability CompanyInventors: Donald James Curry, Ujval J. Kapasi
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Patent number: 8438365Abstract: A method of loading data into register files that correspond to respective execution units within a data-parallel processor. After receiving a first set of parameters that specify a subset of data within a first memory, the first set of parameters are compared to a plurality of sets of conditions that correspond to respective patterns of data. The first set of parameters is then converted to a second set of parameters in accordance with one of the sets of conditions satisfied by the first set of parameters. A sequence of memory addresses are generated based on the second set of parameters. Data is retrieved from locations within the first memory specified by the sequence of memory addresses and loaded into register files that correspond to respective execution units within a processor.Type: GrantFiled: October 9, 2007Date of Patent: May 7, 2013Assignee: Calos Fund Limited Liability CompanyInventor: Timothy J. Southgate
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Patent number: 8433830Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.Type: GrantFiled: June 10, 2012Date of Patent: April 30, 2013Assignee: Calos Fund Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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Patent number: 8412917Abstract: Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer paths are dynamically determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. In addition, embodiments include an integrated-circuit processing device operable to execute operations in parallel, including the capability of providing confirmation information to potential source lanes, the confirmation information indicating whether the potential source lanes may send data to requested destination lanes during a data-transfer interval.Type: GrantFiled: September 20, 2011Date of Patent: April 2, 2013Assignee: Calos Fund Limited Liability CompanyInventors: Brucek Khailany, William James Dally, Ujval J. Kapasi, Jim Jian Lin
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Patent number: 8332829Abstract: Within a data processing system, one or more register files are assigned to respective states of a graph for each of a plurality of clock cycles. A plurality of edges are inserted to form connections between the states of the graph, with respective weights being assigned to each of the edges. A best route through the graph is then determined based, at least in part, on the weights assigned to the edges.Type: GrantFiled: August 15, 2008Date of Patent: December 11, 2012Assignee: Calos Fund Limited Liability CompanyInventor: Peter Mattson
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Patent number: 8321606Abstract: Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.Type: GrantFiled: October 25, 2011Date of Patent: November 27, 2012Assignee: Calos Fund Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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Publication number: 20120254481Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.Type: ApplicationFiled: June 10, 2012Publication date: October 4, 2012Applicant: Calos Fund Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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Patent number: 8259807Abstract: A method of encoding a block of data. A first plurality of data in the block of data is assigned a worth based on a first algorithm. A second plurality of data, which is lower in frequency than the first plurality of data, in the block of data is assigned a worth according to a second algorithm. The block of data is assigned a worth based on the worth of the first plurality of data and the second plurality of data. The worth of the block of data is then compared to a threshold value, and subsequently one or more data values of the block of data are adjusted based on the comparison.Type: GrantFiled: August 15, 2008Date of Patent: September 4, 2012Assignee: Calos Fund Limited Liability CompanyInventor: Yipeng Liu
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Patent number: 8219723Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.Type: GrantFiled: October 18, 2011Date of Patent: July 10, 2012Assignee: Calos Fund Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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Patent number: 8213509Abstract: A method of estimating motion is disclosed. A first plurality of candidates is identified in a reference frame, wherein the total area occupied by the first plurality of candidates is substantially smaller than that of the reference frame. A first refinement search is then performed based, at least in part, on the first plurality of candidates. One or more best candidates are then identified based, at least in part, on the first refinement search. Finally, motion data is encoded based, at least in part, on the one or more best candidates.Type: GrantFiled: October 9, 2007Date of Patent: July 3, 2012Assignee: Calos Fund Limited Liability CompanyInventors: Ujval J. Kapasi, Amit Gulati, John Sievers
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Publication number: 20120042100Abstract: Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.Type: ApplicationFiled: October 25, 2011Publication date: February 16, 2012Applicant: Calos Fund, Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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Publication number: 20120036288Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.Type: ApplicationFiled: October 18, 2011Publication date: February 9, 2012Applicant: Calos Fund, Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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Patent number: 8112591Abstract: A concurrent and asynchronous system may be managed by monitoring the performance of a plurality of operations that access a designated region of memory. In that region of memory, an occurrence of a potentially non-deterministic event can be detected when at least one of the operations is a write operation. The occurrence of the potentially non-deterministic event may then be recorded.Type: GrantFiled: December 9, 2008Date of Patent: February 7, 2012Assignee: Calos Fund, Limited Liability CompanyInventors: David Goodwin, Peter Mattson
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Publication number: 20120011349Abstract: Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer pats are determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Applicant: Calos Fund Limited Liability CompanyInventors: Brucek Khailany, William James Dally, Ujval J. Kapasi, Jim Jian Lin, Raghunath Rao, DeForest Tovey, Mark Rygh, Jung-Ho Ahn
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Patent number: 8051223Abstract: In an embodiment, buffer constructs may be generated to be associated with any one of multiple mutually exclusive states, including an open state and a closed state. When the buffer construct is in the closed state, the region of memory represented by the buffer construct is made accessible to one or more direct memory access (DMA) operations. Upon completion of the one or more DMA operations, the buffer construct transitions from the closed state to the open state. The region of memory represented by the buffer construct is made accessible for use with one or more cache operations when the buffer construct is in the open state, so that the one or more cache operations are not in conflict with the one or more DMA operations.Type: GrantFiled: December 9, 2008Date of Patent: November 1, 2011Assignee: Calos Fund Limited Liability CompanyInventors: Peter Mattson, David Goodwin
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System and method for using a shared buffer construct in performance of concurrent data-driven tasks
Patent number: 8041852Abstract: A computer system is provided that utilizes a buffer construct to manage memory access operations to a region of memory. The buffer construct may correspond to a data item or structure that represents a region of memory. Each task may control the buffer construct exclusively of other tasks, so that the region of memory that is represented by the buffer construct is only available to the controlling task. Another task that requires access to the region of memory must wait until the controlling task makes the buffer construct available. The controlling task makes the buffer construct available only when DMA or other memory access operations that are in progress become complete. In this way, the buffer construct acts as a token that synchronizes each of the concurrent tasks execution and ensures mutually exclusive access to the common region of memory.Type: GrantFiled: December 9, 2008Date of Patent: October 18, 2011Assignee: Calos Fund Limited Liability CompanyInventors: Peter Mattson, David Goodwin