Abstract: A convolution operation method and a processing device for performing the same are provided. The method is performed by a processing device. The processing device includes a main processing circuit and a plurality of basic processing circuits. The basic processing circuits are configured to perform convolution operation in parallel. The technical solutions disclosed by the present disclosure can provide short operation time and low energy consumption.

Abstract: The present disclosure provides a neural network computation device and a neural network computation method. The device is configured to perform artificial neural network training operations including neural network multi-layer training operations. The present disclosure has technical effects of low cost and low energy consumption.

Abstract: The present disclosure discloses a data processing method and related products, in which the data processing method includes: generating, by a general-purpose processor, a binary instruction according to device information of an AI processor, and generating an AI learning task according to the binary instruction; transmitting, by the general-purpose processor, the AI learning task to the cloud AI processor for running; receiving, by the general-purpose processor, a running result corresponding to the AI learning task; and determining, by the general-purpose processor, an offline running file according to the running result, where the offline running file is generated according to the device information of the AI processor and the binary instruction when the running result satisfies a preset requirement. By implementing the present disclosure, the debugging between the AI algorithm model and the AI processor can be achieved in advance.

Abstract: The present disclosure provides a multi-purpose heat sink, a method of manufacturing the same, a board card, and a multi-purpose heat sink platform, where the multi-purpose heat sink is composed of a bracket (310) and heat dissipation components. The cost of the multi-purpose heat sink in the present disclosure is low.

Abstract: Disclosed is a heat dissipation device including a base, a plurality of heat pipes and a heat dissipation structure. The base includes a support plate, a plurality of through-pipe grooves are arranged in the support plate. Each heat pipe includes a heat absorption section and a heat transfer section connected to the heat absorption section, where the heat absorption section is arranged in the through-pipe grooves and at least one heat transfer section of the heat pipe is away from the support plate in the perpendicular direction to the support plate. The heat dissipation structure is arranged on the first surface of the support plate, and the heat transfer section of the plurality of heat pipes extends into the interior of the heat dissipation structure and thermally contacts the heat dissipation structure. The heat dissipation device of the present disclosure dissipates heat faster.

Abstract: An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

Abstract: An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

Abstract: An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

Abstract: An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

Abstract: An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

Abstract: An integrated circuit chip device and related products are provided. The integrated circuit chip device is used for performing a multiplication operation, a convolution operation or a training operation of a neural network. The device has the advantages of small calculation amount and low power consumption.

Abstract: A computing device and related products are provided. The computing device is configured to perform machine learning calculations. The computing device includes an operation unit, a controller unit, and a storage unit. The storage unit includes a data input/output (I/O) unit, a register, and a cache. Technical solution provided by the present disclosure has advantages of fast calculation speed and energy saving.

Abstract: The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.

Abstract: The present disclosure discloses an integrated computing apparatus, a machine learning computing apparatus, a neural network chip, a board card, an electronic device, and a method. The integrated computing apparatus is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The integrated computing apparatus interacts with other processing apparatus to jointly complete a user-specified computing operation. The combined processing apparatus further includes a storage apparatus. The storage apparatus is connected to the integrated computing apparatus and other processing apparatus, respectively. The storage apparatus is used to store data of the integrated computing apparatus and other processing apparatus. The solution of the present disclosure starts and/or shuts down circuits in accordance with a predetermined rule, thus avoiding excessive transient current caused by starting the circuits at the same time.

Abstract: Aspects for Long Short-Term Memory (LSTM) blocks in a recurrent neural network (RNN) are described herein. As an example, the aspects may include one or more slave computation modules, an interconnection unit, and a master computation module collectively configured to calculate an activated input gate value, an activated forget gate value, a current cell status of the current computation period, an activated output gate value, and a forward pass result.

Abstract: The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.

Abstract: The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.

Abstract: Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.

Abstract: The present disclosure provides a network off-line model processing method, an artificial intelligence processing device and related products, where the related products include a combined processing device. The combined processing device includes the artificial intelligence processing device, a general-purpose interconnection interface, and other processing devices, where the artificial intelligence processing device interacts with the other processing devices to jointly complete computation designated by users. The embodiments of the present disclosure can accelerate the operation of the network off-line model.

Abstract: The present disclosure provides a data processing method and an apparatus and a related product. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By utilizing the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.