Abstract: A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1st time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the ith time, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i?1)th time.

Abstract: A hot-swap protection circuit includes: a hot-swap circuit, a hot-swap detection circuit, and an N-well generation circuit, where the hot-swap detection circuit is configured to detect whether hot-swap is performed on the hot-swap circuit, and feed back a detection result to the N-well generation circuit; and the N-well generation circuit is configured to receive the detection result fed back by the hot-swap detection circuit, and output a control signal according to the detection result, to protect the hot-swap circuit. The hot-swap detection circuit is used to detect whether hot-swap is performed on the hot-swap circuit, and the detection result is fed back to the N-well generation circuit, so that the N-well generation circuit outputs a control signal according to the detection result fed back by the hot-swap detection circuit, to protect the hot-swap circuit, thereby preventing the hot-swap of the hot-swap circuit from burning a host or a peripheral device.

Abstract: The present invention relates to a chip power supply method and a chip, where configuration memory array provides configuration voltage to an NMOS transmission gate, and an LDO circuit supplies power to the chip. The method includes: determining that a working state of the chip switches from a first state to a second state, where the first state and the second state are separately an initial mode, a program mode or a user mode; and adjusting, according to the working state of the chip, a configuration bit to adjust an output voltage of the LDO circuit. The present invention reduces power dissipation of the chip during memory configuration, and improves working performance thereof during the user mode.

Abstract: A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.

Abstract: An integrated circuit chip includes at least one driver circuit of single-ended structure and the first drive circuit, the first drive circuit and the at least one driver circuit of single-ended structure have the same structure, the first drive circuit includes a plurality of parallel-connected PMOS tubes and a plurality of parallel-connected NMOS tubes, the plurality of parallel-connected PMOS tubes connect the plurality of parallel-connected NMOS tube in series at a first node. After impedance calibration has been conducted, the chip confines a first impedance calibration code and a second impedance calibration code, and controls the at least one driver according to the first impedance calibration code and the second impedance calibration code; the first reference voltage is preferably configured to ¾ times of the supply voltage VDD, and the second reference voltage is preferably configured to ¼ times of the supply voltage VDD.

Abstract: An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

Abstract: A circuit and method of power on initialization for a configuration memory of an FPGA. The circuit includes: a decoding circuit, a driving circuit, and a configuration memory, where when 0 is written for the 1st time, the decoding circuit turns on a word line corresponding to an address in the configuration memory, and the driving circuit writes content of the word line into 0; and when 0 is written for the ith time, the decoding circuit turns on at least one word line corresponding to at least one address in the configuration memory, and the driving circuit writes content of each word line in the at least one word line into 0, the number of the at least one address being less than or equal to a sum of addresses that have completed writing of 0 for the previous (i?1)th time.

Abstract: The present invention relates to a chip power supply method and a chip, where configuration memory array provides configuration voltage to an NMOS transmission gate, and an LDO circuit supplies power to the chip. The method includes: determining that a working state of the chip switches from a first state to a second state, where the first state and the second state are separately an initial mode, a program mode or a user mode; and adjusting, according to the working state of the chip, a configuration bit to adjust an output voltage of the LDO circuit. The present invention reduces power dissipation of the chip during memory configuration, and improves working performance thereof during the user mode.

Abstract: A hot-swap protection circuit includes: a hot-swap circuit, a hot-swap detection circuit, and an N-well generation circuit, where the hot-swap detection circuit is configured to detect whether hot-swap is performed on the hot-swap circuit, and feed back a detection result to the N-well generation circuit; and the N-well generation circuit is configured to receive the detection result fed back by the hot-swap detection circuit, and output a control signal according to the detection result, to protect the hot-swap circuit. The hot-swap detection circuit is used to detect whether hot-swap is performed on the hot-swap circuit, and the detection result is fed back to the N-well generation circuit, so that the N-well generation circuit outputs a control signal according to the detection result fed back by the hot-swap detection circuit, to protect the hot-swap circuit, thereby preventing the hot-swap of the hot-swap circuit from burning a host or a peripheral device.

Abstract: A charge pump circuit includes a first PMOS transistor and a first NMOS transistor that are connected in series to a main charging and discharging circuit, where a grid electrode of the first PMOS transistor is controlled by an inverted signal of a first control signal. A grid electrode of the first NMOS transistor is controlled by a second control signal. The circuit further includes a second PMOS transistor that is located in a first branch circuit, where a grid electrode of the second PMOS transistor is controlled by the first control signal; and includes a second NMOS transistor that is located in a second branch circuit, where a grid electrode of the second NMOS transistor is controlled by an inverted signal of the second control signal. The embodiments resolve a problem of leakage currents.

Abstract: A buffer circuit includes a buffer group including an odd number of cascade buffers, where the buffers may be different from each other; a PMOS transistor and an NMOS transistor; where a source of the PMOS transistor is coupled to a power source, a drain thereof is connected to an output terminal of the buffer group, and a gate thereof is connected to an input terminal of the buffer group; a source of the NMOS transistor is coupled to ground, a drain thereof is connected to the output terminal of the buffer group, and a gate thereof is connected to the input terminal of the buffer group.

Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.

Abstract: A structure of a multi-mode supported and configurable six-input look-up table (LUT), and a field-programmable gate array (FPGA) device. The six-input LUT has six signal input ends and two signal output ends. The six-input LUT includes: a first five-input LUT, a second five-input LUT, a first multiplexer, and a second multiplexer. The first five-input LUT outputs a first output signal according to five data signals input by five signal input ends of the six-input LUT, where the first output signal is output by a first signal output end of the six-input LUT; the second five-input LUT outputs a second output signal according to the five data signals input by the five signal input ends of the six-input LUT; and the first multiplexer outputs a control signal according to a set configuration mode, to control the second multiplexer to output the first output signal or the second output signal.

Abstract: A configuration structure and method of a block memory. The configuration structure includes a first port, a second port, an ECC module, and an FIFO module; the ECC module includes an ECC encoder and an ECC decoder; the FIFO module is used for setting the first clock enable terminal and the second clock enable terminal, so as to make the read clock synchronous or asynchronous with and the write clock of the block memory. The read width and the write width of the block memory can be independently configured, and the block memory has built-in an ECC function and a FIFO function, and can be cascaded to a block memory with larger storage space without consuming additional logic resource.

Abstract: A carry-skip one-bit full adder and a field programmable gate array device, the full adder includes: a first multiplexer, a second multiplexer, and an adder, the first multiplexer includes a first addend input end and a first constant input end configured to input a first constant to the first multiplexer; the second multiplexer includes a second addend input end and a second constant input end configured to input a second constant to the second multiplexer; when the first addend input end is not used for input of a first addend, and/or when the second addend input end is not used for input of a second addend, the first multiplexer selects to output the first constant input, and the second multiplexer selects to output the second constant input.

Abstract: An extensible configurable FPGA storage structure and an FPGA device, where the FPGA storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.

Abstract: A simulation verification method for Field Programmable Gate Array (FPGA) function modules and a system thereof. The method includes: generating all test cases by enumerating all parameter characteristics of FPGA function modules; generating, according to an input type and input parameter characteristics of an FPGA function module under test, a simulation test bench matching configuration of the corresponding FPGA function module under test; and randomly generating, by the simulation test bench, a test stimulus and a corresponding expected output according to the input parameter characteristics of the FPGA function module under test, comparing the expected output with an actual output obtained after the test stimulus is applied to the test case corresponding to the FPGA function module under test, and outputting a test report of the FPGA function module under test according to a comparison result.

Abstract: A power-on reset (POR) circuit includes an RC circuit; a Schmitt trigger, an inverter, and a first PMOS tube. A power supply voltage charges a capacitor through the RC circuit. When a voltage of the capacitor reaches a first threshold, the Schmitt trigger reverses, a first level is output. The POR circuit includes a discharge circuit used to detect a glitch of the power supply voltage, and output a first signal to an input end of the Schmitt trigger when the glitch is detected. The first signal allows the Schmitt trigger to reverse again to output a second level, so as to turn off the first PMOS tube through the inverting amplifier. When the power supply voltage rises along an oblique line again, the Schmitt trigger reverses, and the first level is output, so as to reset the system where the circuit is.