Abstract: A method of making a package for an integrated circuit die. In one embodiment the method comprises providing a semiconductor wafer having a plurality of integrated circuit die formed thereon, each integrated circuit die having a first surface and a second surface opposite the first surface and a plurality of bonding pads formed on the first surface, prior to dicing the semiconductor wafer, selectively applying a curable material over a portion of the first surface of an integrated circuit die formed on the wafer without covering the plurality of bonding pads, curing the curable material and dicing the semiconductor wafer to separate the integrated circuit die from other integrated circuit die formed upon the wafer.

Abstract: A method of encapsulating a plurality of IC chips attached to a lead frame strip that includes an outer frame and a plurality of vertical and horizontal connecting bars attached to the outer frame in a manner that defines a plurality of inner frames arranged in a matrix pattern within the outer frame, each inner frame including an area where an IC chip from the plurality of IC chips is attached.

Abstract: The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).

Abstract: The present invention relates to a new method for sawing a moulded leadframe package (1) into individual integrated circuits (11). In the present invention sawing of the moulded leadframe package (1) is done on the leads (13) instead of on the connecting bar (14) resulting in less heat being generated during cutting. This results in higher cutting speed and longer dicing blade life.

Abstract: There is disclosed a flip-chip-type method of assembling semiconductor devices. The proposed invention offer one step encapsulation process to promote adhesion of die to the lead finger and prevent the potential of shorts from developing between the adjacent bumps (13) or lead fingers. Conventional mold compound (15) is used to reduce localized stress causes by coefficient of thermal expansion (CTE) mismatch between the die (11) and substrate, or the lead frame (12). This is particularly favorable in promoting greater mechanical robustness of the semiconductor devices. With one step encapsulation process proposed by the present invention, manufacturing process is made simpler, faster and relatively cheaper.